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Hi,I'm using the CyConsloe to test the loopback between FPGA and the cy68013a。I just send data to the EP2 endpoint and loopback to the EP6 endpoint The following is my firmware ,is there something wrong with my firmware
void TD_Init(void) // Called once at startup
{
// set the CPU clock to 24MHz
CPUCS =0x08;
SYNCDELAY;
// set the slave FIFO interface to 48MHz,SYNC,IFCLK output
IFCONFIG = 0xE3;
SYNCDELAY;
REVCTL = 0x03;
SYNCDELAY; // Registers which require a synchronization delay, see section 15.14
// FIFORESET FIFOPINPOLAR
// INPKTEND OUTPKTEND
// EPxBCH:L REVCTL
// GPIFTCB3 GPIFTCB2
// GPIFTCB1 GPIFTCB0
// EPxFIFOPFH:L EPxAUTOINLENH:L
// EPxFIFOCFG EPxGPIFFLGSEL
// PINFLAGSxx EPxFIFOIRQ
// EPxFIFOIE GPIFIRQ
// GPIFIE GPIFADRH:L
// UDMACRCH:L EPxGPIFTRIG
// GPIFTRIG
// Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
// ...these have been replaced by GPIFTC[B3:B0] registers
// default: all endpoints have their VALID bit set
// default: TYPE1 = 1 and TYPE0 = 0 --> BULK
// default: EP2 and EP4 DIR bits are 0 (OUT direction)
// default: EP6 and EP8 DIR bits are 1 (IN direction)
// default: EP2, EP4, EP6, and EP8 are double buffered
// we are just using the default values, yes this is not necessary...
EP1OUTCFG &= 0x7F; //set invalid
EP1INCFG &= 0x7F;
SYNCDELAY; // see TRM section 15.14
EP2CFG = 0xA2; //set EP2 valid, out, bulk, 512, double buffer.
SYNCDELAY;
EP4CFG &= 0x7F; //set invalid.
SYNCDELAY;
EP6CFG = 0xE2; //set EP6 valid, in, bulk, 512, double buffer.
SYNCDELAY;
EP8CFG &= 0x7F; //set invalid.
SYNCDELAY;
FIFORESET = 0x80; // reset all FIFOs
SYNCDELAY;
FIFORESET = 0x02;
SYNCDELAY;
FIFORESET = 0x04;
SYNCDELAY;
FIFORESET = 0x06;
SYNCDELAY;
FIFORESET = 0x08;
SYNCDELAY;
FIFORESET = 0x00;
SYNCDELAY;
OUTPKTEND=0x82; //arm EP2 two times
SYNCDELAY;
OUTPKTEND=0x82;
SYNCDELAY;
EP2FIFOCFG = 0x11; //EP2 autoout=1 wordwide=1;
SYNCDELAY;
EP6FIFOCFG = 0x0D; //EP6 autoin=1 zerolength=1 wordwide=1;
SYNCDELAY;
PINFLAGSAB = 0xE0; // FLAGB as EP6 full flag,
SYNCDELAY;
PINFLAGSCD = 0x08; // FLAGC as EP2 empty flag
SYNCDELAY;
PORTACFG = 0x00; // won't generally need FLAGD
SYNCDELAY;
FIFOPINPOLAR = 0x00; // set all slave FIFO interface pins as active low
SYNCDELAY;
EP6AUTOINLENH = 0x02;
SYNCDELAY;
EP6AUTOINLENL = 0x00;
SYNCDELAY;
}
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