Hi, 

I am working on Cy7C680-13A usb 2.0 high speed controller. I would like to brief on my system before coming into the problem. 

My system has one endpoint (EP2), configured as IN endpoint. 

I have used the following lines of codes to enumerate device as a full speed, so that even I plug my USB 2.0 high speed device into a USB high speed host, the device will get enumerated as a full speed, and not high speed, which is a requirement of my project. 

USBCS |= 0x08;

EZUSB_Delay(1500);

CT1 |= 0x02;

USBCS &=0xF7; 

I am trying to interface an externel master (a cmos camera sensor) to the usb device controller in asynchronous mode. The clock from the externel master is connected to SLWR signal, where I am expecting the external master to write to the IN endpoint FIFO. The SLWR pin is toggled at the rate of 320ns. 

Now the problem is,

For the below mentioned code written in TD_Poll( ), I am not able to get the USB device enumerated. 

while(!(EP24FIFOFLGS & 0x04)); //check for programmable flag in EP2

{

SYNCDELAY;

EP2BCH = 0x00;            //commiting the packet

SYNCDELAY;

EP2BCL = 0x40;

SYNCDELAY;

}

I find that the program is waiting indefinitely at the while loop mentioned in line 1 (things work fine once I comment of the while loop). 

Here is how I have configured my programmable flag in TD_Init ( ). 

EP2FIFOPFH = (bmBIT7 | bmBIT6);          SYNCDELAY;//setting DECIS and PKTSTAT

EP2FIFOPFL = 0x40;                             SYNCDELAY;

In the above programmable flag configuration, I expect the TD_Poll( ) to come out of while loop once a size of 64 bytes gets filled in EP2. But this is not happening. The program is getting hang inside the while loop mentioned above. 

Why is this happening ? Am I missing anything in programmable flag ? 

Thank You

 Hi, 

I would like to brief the above issue once again: 

What all registers are to be considered when we need to work on programmable flag for FX2LP device. ? 

Is there any application note programmable FIFO flag ? 

Thank You

 Hi,

Why don't you try 

if(EP24FIFOFLGS & 0x04)

{

SYNCDELAY;

EP2BCH = 0x00;            //commiting the packet

SYNCDELAY;

EP2BCL = 0x40;

SYNCDELAY;

}

Since the TD_POLL() is called repetedly, will this not do the job? Just a suggestion.

Regards,

Gayathri

 Hi, 

I tried the code with both programmable and full flag, but found that both are not getting asserted.  

if(EP24FIFOFLGS & 0x04)

{

SYNCDELAY;

EP2BCH = 0x00;            //commiting the packet

SYNCDELAY;

EP2BCL = 0x40;

SYNCDELAY;

}

Do I need to have any hardware handshaking with FLAGx pins to check the status in FIFO ? 

Thank You

 Hi,

I believe what you want to achieve with FX2LP in Slave mode is that as soon as the EP2 gets filled with 64bytes of data it should be committed to the USB side. Are you keeping FX2LP in manual mode? If you want any data modification, then you may choose FX2LP to be in Slav emanual mode. If so please check if there is anything that you are issing in the initialization sequence as in http://www.cypress.com/?rID=45850. Refer the firmware for Slave Manual mode in the same.

If no data modification is required. why don't you go for auto mode, and keep AUTOINLENH/L for EP2 as 64 bytes?

Regards,

Gayathri

 Hi, 

Thanks for the reply. 

I dont need a data modification, so I am going for a auto mode. The application note AN58069 is similar to the interface I use (SLWR interfaced to gated clock). 

regards

Gigin

Cool 

Regards,

Gayathri