streamin and loopback of AN61345 not giving correct output

	usman posted on 09 Sep 2012 3:12 AM PST Member 3 Forum Posts

hi,

i am using FX2lP 56-pin package.
I have implemented loopback and streamin examples from the AN61345 . Spartan3E FPGA and fx2lp configuration is done according to the AN61345 .
slave.c is downloaded successfully in the eeprom and detected on Cypress USB Console.
i have downloaded vhdl files for loopback in the fpga.No changes are done in slave.c firmware and vhdl files except pins assignment.

----------------------------------
Problem:1 (for LOOPBACK example )
----------------------------------

1) when i bulkout hex "01" 512 bytes using Cypress USB Console app,result in bulkin is "02" 512 bytes. correct result.
2) when i bulkout hex "02" 512 bytes using Cypress USB Console app,result in bulkin is "03" 512 bytes. correct result.
     ....... and so on for bulkouts 03,04,05,06,08,09,0A,0B....and any input which exclude "07" or "0F" i got correct result but
3) when i bulkout hex "07" 512 bytes using Cypress USB Console app,result in bulkin is strange :

    00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
    00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
    00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
    00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
    00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
    00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
    00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
    00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
    00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
    00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
    00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
    00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
    00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
    00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
    00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
    00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
    00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
    00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
    00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
    00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
    00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
    00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
    00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
    00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
    00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
    00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
    00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
    00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
    00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
    00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
    00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
    00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10

4) when i bulkout hex "17" 512 bytes using Cypress USB Console app,result in bulkin is " 10 20 "( replace " 00 10 " with "10 20" in above output representation) incorrect result
5) when i bulkout hex "27" 512 bytes using Cypress USB Console app,result in bulkin is " 20 30 "( replace " 00 10 " with "20 30" in above output representation)incorrect result
6) when i bulkout hex "37" 512 bytes using Cypress USB Console app,result in bulkin is " 30 40 "( replace " 00 10 " with "30 40" in above output representation)incorrect result
7) when i bulkout hex "47" 512 bytes using Cypress USB Console app,result in bulkin is " 40 50 "( replace " 00 10 " with "40 50" in above output representation)incorrect result
      and so on in same manner up "97".
8) when i bulkout hex "0F" 512 bytes using Cypress USB Console app,result in bulkin is " 08 18 "( replace " 00 10 " with "08 18" in above output representation) incorrect result

---------------------------------------
Problem 2 : (for STREAMIN example ):
---------------------------------------

i have downloaded vhdl files of streamin example in fpga and result is not correct ON BULK IN :

08 09 0A 0B 0C 0D 0E 0F 08 09 0A 0B 0C 0D 0E 0F
18 19 1A 1B 1C 1D 1E 1F 18 19 1A 1B 1C 1D 1E 1F
28 29 2A 2B 2C 2D 2E 2F 28 29 2A 2B 2C 2D 2E 2F
38 39 3A 3B 3C 3D 3E 3F 38 39 3A 3B 3C 3D 3E 3F
48 49 4A 4B 4C 4D 4E 4F 48 49 4A 4B 4C 4D 4E 4F
58 59 5A 5B 5C 5D 5E 5F 58 59 5A 5B 5C 5D 5E 5F
68 69 6A 6B 6C 6D 6E 6F 68 69 6A 6B 6C 6D 6E 6F
78 79 7A 7B 7C 7D 7E 7F 78 79 7A 7B 7C 7D 7E 7f
88 89 8A 8B 8C 8D 8E 8F 88 89 8A 8B 8C 8D 8E 8F
98 99 9A 9B 9C 9D 9E 9F 98 99 9A 9B 9C 9D 9E 9F
A8 A9 AA AB AC AD AE AF A8 A9 AA AB AC AD AE AF
B8 B9 BA BB BC BD BE BF B8 B9 BA BB BC BD BE BF
C8 C9 CA CB CC CD CE CF C8 C9 CA CB CC CD CE CF
D8 D9 DA DB DC DD DE DF D8 D9 DA DB DC DD DE DF
E8 E9 EA EB EC ED EE EF E8 E9 EA EB EC ED EE EF
F8 F9 FA FB FC FD FE FF F8 F9 FA FB FC FD FE FF
08 09 0A 0B 0C 0D 0E 0F 08 09 0A 0B 0C 0D 0E 0F
18 19 1A 1B 1C 1D 1E 1F 18 19 1A 1B 1C 1D 1E 1F
28 29 2A 2B 2C 2D 2E 2F 28 29 2A 2B 2C 2D 2E 2F
38 39 3A 3B 3C 3D 3E 3F 38 39 3A 3B 3C 3D 3E 3F
48 49 4A 4B 4C 4D 4E 4F 48 49 4A 4B 4C 4D 4E 4F
58 59 5A 5B 5C 5D 5E 5F 58 59 5A 5B 5C 5D 5E 5F
68 69 6A 6B 6C 6D 6E 6F 68 69 6A 6B 6C 6D 6E 6F
78 79 7A 7B 7C 7D 7E 7F 78 79 7A 7B 7C 7D 7E 7f
88 89 8A 8B 8C 8D 8E 8F 88 89 8A 8B 8C 8D 8E 8F
98 99 9A 9B 9C 9D 9E 9F 98 99 9A 9B 9C 9D 9E 9F
A8 A9 AA AB AC AD AE AF A8 A9 AA AB AC AD AE AF
B8 B9 BA BB BC BD BE BF B8 B9 BA BB BC BD BE BF
C8 C9 CA CB CC CD CE CF C8 C9 CA CB CC CD CE CF
D8 D9 DA DB DC DD DE DF D8 D9 DA DB DC DD DE DF
E8 E9 EA EB EC ED EE EF E8 E9 EA EB EC ED EE EF
F8 F9 FA FB FC FD FE FF F8 F9 FA FB FC FD FE FF

No changes are done in the vhdl and fx2lp firmware.Same files work correctly on the development kit hardware but when i implement these files on my own
hardware, the strange result is above for both examples...!

--------------
QUESTIONS:
--------------

1) the problem which comes in loopback when input containig hex 7 or F. According to my observations of the above outputs, FD.3 data line gives zero instead of '1' at the bulkin when bulkout has
combination containig 7 or F ? Also note the streamin output which is giving 1 at FD.3 line ?
2)what can be the possible problem? FD[7:0] are correctly connected to fpga.
3) is this a hardware issue or software ?

plz help.

thanks

Re: streamin and loopback of AN61345 not giving correct output

	aasi posted on 13 Sep 2012 06:08 PM PST Cypress Employee 1090 Forum Posts

Hook up a logic analyzer/oscilloscope on the interface to look at what the FPGA is sending. Especially probe the FD.3 line.

That should tell you more...

If it works on the kit and not on your board then the issue is most probably hardware related than anything else...

Regards,

Anand

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streamin and loopback of AN61345 not giving correct output

Re: streamin and loopback of AN61345 not giving correct output