Hi all

I am designing an application using CY7C68013A that must support high-bandwidth isochronous OUT transfers. Data should be moved out of CY7C68013A to a FPGA. I have implemented device descriptors, the host recognizes the CY7C68013A and loads driver (USB audio), and when I run an application on host (audio player), it seems to send out the data just. The interface between CY7C68013A and FPGA is still TBD, so on this early stage I just want to make sure that the correct data arrives to endpoint. Can someone post a minimalistic example of how I setup the registers, and check the arrived data packets and then discard them?

 Hi,

 You could look at the streamer example in C:\Cypress\Cypress Suite USB 3.4.7\Firmware\CyStreamer after installing SuiteUSB(http://www.cypress.com/?rID=34870).

Regards

Prajith

I did so.

The examples are not very helpful. They seem to have "all in one", and it is hard to find out what each piece  of code is doing (even with TRM help).

I am trying to learn Fx2LP step-by-step, starting from simple things - first do not do any external I/O at all. Still cannot figure out how to do very simple thing - once a packet arrives, toggle an output line. I have tried different register settings, but I only get EMPTY  bit for EP2 in  EP2468STAT either constantly on, or constantly off.

Here are the relevant pieces of code I am using:

Initialization:

void main_init()
{

    //debug pin
    OED = 0x02;
    P3_1 = 1;

    REVCTL = 3;
    IFCONFIG = 0x00;
    SYNCDELAY();
    // Only using endpoint 2, zero the valid bit on all others
    EP1OUTCFG = EP1INCFG = EP4CFG = EP6CFG = EP8CFG = 0x00;
    SYNCDELAY();
    EP2FIFOCFG = 0x00;
    SYNCDELAY();

    printf("Initialization Done.\n");

}

This is called when host selects an interface:

BOOL handle_set_interface(BYTE ifc, BYTE alt_ifc)
{
    interface = ifc;
    alt = alt_ifc;
    if (!alt) {
        EP2CFG = 0;
    } else {
        //       Valid      Out        ISO        1024       DoubleBuf
        EP2CFG = (1 << 7) | (0 << 6) | (1 << 4) | (1 << 3) | (2 << 0);
        SYNCDELAY();
        // OUT endpoints do NOT come up armed
        EP2BCL = 0x80; // arm first buffer by writing BC w/skip=1
        SYNCDELAY();
        EP2BCL = 0x80; // arm second buffer by writing BC w/skip=1
    }
   
    return TRUE;
}
 

This is called from main() endless loop, when there are no EP0 requests to service:

void main_loop()
{
    if (alt) {
        if(!(EP2468STAT & bmEP2EMPTY)) {
            P3_1 ^= 1;
            EP2BCL = 0x80;
        }
    }
}
 

With this code,  EMPTY  bit in EP2468STAT  is always cleared, regardless of if any data is sent to EP2.

If I change EP2FIFOCFG to 0x10,  EMPTY  bit in EP2468STAT  is always set, regardless of if any data is sent to EP2.

Correction:

With this code,  EMPTY  bit in EP2468STAT  is always set, regardless of if any data is sent to EP2.

If I change EP2FIFOCFG to 0x10,  EMPTY  bit in EP2468STAT  is always cleared, regardless of if any data is sent to EP2.

 Please refer TD_INIT() and TD_LOOP() portion of code in GPIF manual Mode eg: / GPIF auto mode eg: according to your application http://www.cypress.com/?rID=45850.

Regards,

Gayathri