The follwing are based on slave fifo mode.I want to transfer the data to the EP0 ,then exchange the data between EP0 and EP6 under the vender command .I read the data from EP6, just as the bulk loop example,can everybody tell me weather the procedure wright or wrong ?Thanks
void TD_Init(void) // Called once at startup
{
// set the CPU clock to 48MHz
CPUCS =0x10;
// set the slave FIFO interface to 48MHz
IFCONFIG = 0xC0;
REVCTL = 0x03;
SYNCDELAY;
// Registers which require a synchronization delay, see section 15.14
// FIFORESET FIFOPINPOLAR
// INPKTEND OUTPKTEND
// EPxBCH:L REVCTL
// GPIFTCB3 GPIFTCB2
// GPIFTCB1 GPIFTCB0
// EPxFIFOPFH:L EPxAUTOINLENH:L
// EPxFIFOCFG EPxGPIFFLGSEL
// PINFLAGSxx EPxFIFOIRQ
// EPxFIFOIE GPIFIRQ
// GPIFIE GPIFADRH:L
// UDMACRCH:L EPxGPIFTRIG
// GPIFTRIG
// Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
// ...these have been replaced by GPIFTC[B3:B0] registers
// default: all endpoints have their VALID bit set
// default: TYPE1 = 1 and TYPE0 = 0 --> BULK
// default: EP2 and EP4 DIR bits are 0 (OUT direction)
// default: EP6 and EP8 DIR bits are 1 (IN direction)
// default: EP2, EP4, EP6, and EP8 are double buffered
// we are just using the default values, yes this is not necessary...
EP1OUTCFG &= 0x7F; //set invalid
EP1INCFG &= 0x7F;
SYNCDELAY; // see TRM section 15.14
EP2CFG = 0x7F; //set invalid
SYNCDELAY;
EP4CFG &= 0x7F; //set invalid.
SYNCDELAY;
EP6CFG = 0xE2; //set EP6 valid, in, bulk, 512, double buffer.
SYNCDELAY;
EP8CFG &= 0x7F;
SYNCDELAY; //set invalid.
FIFORESET = 0x80; // reset all FIFOs
SYNCDELAY;
//FIFORESET = 0x82;
// SYNCDELAY;
// FIFORESET = 0x84;
// SYNCDELAY;
FIFORESET = 0x02;
SYNCDELAY;
FIFORESET = 0x06;
SYNCDELAY;
FIFORESET = 0x00;
SYNCDELAY;
EP6FIFOCFG = 0x0D;//Autoin=1 Wordwide=1 Zerolength=1
SYNCDELAY;
EP6AUTOINLENH = 0x00;
SYNCDELAY;
EP6AUTOINLENL = 0x04;//just 4 bytes
// enable dual autopointer feature
AUTOPTRSETUP |= 0x01;
}
The following is Vender command
BOOL DR_VendorCmnd(void)
{
WORD i;
WORD count;
switch (SETUPDAT[1])
{
case VD_COMMAND:
if(!(EP0CS&0x02))
{ // check EP0 BUSY bit
if(!(EP2468STAT & bmEP6FULL))
{ // check EP6 FULL(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is full
APTR1H = MSB( &EP0BUF );
APTR1L = LSB( &EP0BUF );
AUTOPTRH2 = MSB( &EP6FIFOBUF );
AUTOPTRL2 = LSB( &EP6FIFOBUF );
count = (EP0BCH << 8) + EP0BCL;
// loop EP0OUT buffer data to EP6OUT
for( i = 0x0000; i < count; i++ )
{
// setup to transfer EP0OUT buffer to EP6IN buffer using AUTOPOINTER(s)
EXTAUTODAT2 = EXTAUTODAT1;
}
EP6BCH = EP0BCH;
SYNCDELAY;
EP6BCL = EP0BCL; // arm EP6IN
SYNCDELAY;
EP0BCL = 0x80;
} // re(arm) EP0OUT
break;
}
default:
return(TRUE);
}
EP0CS|=bmHSNAK;
return(FALSE);
}
|