Hello. In the Slave FIFO example, the dmaCfg.count is set to 2 (Slave FIFO channel buffer counts 2). When the data is transferred from U to P, the data is written to the first buffer at the first time and written to the second buffer at the second time. After that, if the Reading from Slave FIFO (SLRD) is not active, the buffer will be always full and no more data can be written. Once the Reading from Slave FIFO starts, the buffers will be clean and ready for the next transfer. Is my understanding right?

Yes. Your understanding is right.

Coming to other question, I am assuming it is "I2C". Please let me know if my assumption is right.

Thanks,

sai krishna.

Hello, sai Krishna,

Thanks

Lehua Chen

Hi Lehua Chen,

You can use I2C both for loading the programm into RAM and for sending commands to your FPGA. Just the slave address will be different from each other.

As you know, I2S is generally used for streaming the audio samples.

Regards,

sai kirshna.

Hi, sai Krishna,

Yes. FX3 boot from the I2C EEPROM that is connected to it.

When you want to send some command to FPGA from PC, you send a command from PC to FX3 over the control endpoint and then in the firmware you parse it and initiate a I2C read from the FPGA connected to FX3.

Regards,

sai krishna.

In this case, both E2PROM and two pins of FPGA will be connected to I2C_GPIO[58] (I2C_SCL) and I2C_GPIO[59]( I2C_SDA). Right?

Thank you

Lehua Chen

Right.