hi,
I am using Win7 + Suite USB 3.4.7 + 68013A PVX 56 + slave FIFO + (FPGA) Cyclone II,
I use CyConsole input" 1 2 3 4 5 6 7 8 9" , to EP2 , but I read "2 4 6 8" from EP6,
half data lose! anyone can help me ? thanks!
below is my firmware and verilog code:
=============================================================
// Called once at startup
CPUCS = 0x10; // CLKSPD[1:0]=10, for 48MHz operation, output CLKOUT
IFCONFIG = 0xE3;
REVCTL=0x01;
// 48 MHz internal clock source, drive IFCLK, synchronous slave FIFO mode
PINFLAGSAB = 0x08; // FLAGA - EP6 FULL flag
SYNCDELAY;
PINFLAGSCD = 0xE0; // FLAGD - EP2 Emtpy flag
SYNCDELAY;
PORTACFG |= 0x80;
EP4CFG = 0x02; //clear the valid bits on ep4 and ep8
SYNCDELAY;
EP8CFG = 0x02;
SYNCDELAY;
EP2CFG = 0xA2; // OUT, 512-bytes, 4x, bulk
SYNCDELAY;
EP6CFG = 0xE2; // IN, 512-bytes, 4x, bulk
SYNCDELAY;
FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions
SYNCDELAY; // see TRM section 15.14
FIFORESET = 0x02; // reset, FIFO 2
SYNCDELAY; //
FIFORESET = 0x04; // reset, FIFO 4
SYNCDELAY; //
FIFORESET = 0x06; // reset, FIFO 6
SYNCDELAY; //
FIFORESET = 0x08; // reset, FIFO 8
SYNCDELAY; //
FIFORESET = 0x00; // deactivate NAK-ALL
// handle the case where we were already in AUTO mode...
// ...for example: back to back firmware downloads...
SYNCDELAY; //
EP2FIFOCFG = 0x00; // AUTOOUT=0, WORDWIDE=0
// core needs to see AUTOOUT=0 to AUTOOUT=1 switch to arm endp's
SYNCDELAY; //
EP2FIFOCFG = 0x10; // AUTOOUT=1, WORDWIDE=0
SYNCDELAY; //
EP6FIFOCFG = 0x0C; // AUTOIN=1, ZEROLENIN=1, WORDWIDE=0, INFM = 1;
SYNCDELAY;
=======================================================================================
module fpga_master
(
input clk,
input rst_n,
input flaga, //EP2 empty flag
input flagd, // EP6 full flag
output reg [1:0] faddr,
output reg sloe,
output reg slrd,
output reg slwr,
inout [7:0]fdata,
output led,
output beep
);
(* noprune *)reg [25:0] counter;
assign led =counter[25];
assign beep =1;
reg link = 0; //link控制三态门
(* noprune *)reg [7:0]fdata_reg = 0;
assign fdata = link ? fdata_reg:8'bz;
(* noprune *)reg [3:0] state = 0;
(* noprune *)reg [31:0] recv_count = 0;
(* noprune *)reg [31:0] send_count = 0;
(* noprune *)reg [7:0] fifodata = 0;
always@(posedge clk)
begin
counter <= counter + 26'b1;
end
(* noprune *) reg [7:0] temp[15:0];
always@(posedge clk)
begin
case(state)
0:
begin
faddr <= 2'b00;
sloe <= 0; // IDLE STATE
link <= 0;
slrd <= 1;
slwr <= 1;
state <= 1;
end
1:
begin
if(flaga == 1) // not empty
begin
slrd <= 0;
state <= 2;
end
else
begin
slrd <= 1;
state <= 0;
end
end
2:
begin
fifodata = fdata;
temp[recv_count] = fdata;
recv_count = recv_count +1;
faddr <= 2'b10; // ep6
link <= 1;
sloe <= 1;
state <= 3;
end
3:
begin
if(flagd == 1) // not full
state <= 4;
else
state <= 3;
fdata_reg <= fifodata;
end
4:
begin
slwr <= 0;
send_count <= send_count +1;
state <= 0;
end
default:
state<=0;
endcase
end
endmodule
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