Hi, I have modified the UVC example to Full HD uncompressed  and still using internal image buffer (no extra hardware). No toggle FID, always using same image data, and i found the period between two transfers increase dramatically after first several transfers finshed (please see attached file), and if i disable all caches,the period will increase even more (more than 4.ms). i thought this is due to the latency of RTOS lib,but is there any way to avoid this? thanks.

is there any demo about this kind of higher resolution application? 

 BULK transfers are bursty in nature, So these kind of delays are expected from the host side. I don't think there is a way to avoid these gaps if we are using BULK transfers. Having a big buffer in the FX3 should save some data but it cannot completely avoid such scenarios.

Going to ISO transfers should help you to avoid these scenarios. There is a example project with ISO transfers as well. Did you get a chance to try that.

Thanks,

Sai Krishna.

 Hi,

Please expand the traffic to let us know if there are lot of NAKs being seen on the bus or if the delay is due to lack of between IN packets.

Regards,

Anand

There is no NRDY, it seems Host is not the transfer initiator in this case (even if Device somehow postpone the transfer), it is up to Deice to initiate another transfer with ERDY, so there would be no NRDY.

please let me know if my understanding is wrong regarding to the bandwidth(no NRDY latency), thanks

Owen Chang,

I did not get your post completley. Could you please explain me your understanding on the bandwidth again.

Thanks,

sai krishna.

 Sorry, let me explain further. I try to build an UVC BULK of uncompressed Full HD example, but once I complete the coding (image data is in memory, not provide by external hardware), I found there is huge delay between last ACK from Host and Device’s ERDY (ref: pictures of previous post). Data payload is 15362 including header, so the last DP is 2 Byte and the EOB of this DP is 1, this EOB will stop Host from initiating next transaction, and the next transaction will be initiated by Device’s ERDY. My question is the latency from last ACK (Host acknowledge this 2B DP) to ERDY (from Device) is too long (4ms), and this will decrease the frame rate, but once I enable all caches (I / D / DMA), the latency down to 1ms. I wonder this is the limitation of FX3, because we can only access hardware via RTOS, lots of code running on the background and decrease performance under certain cases.

Perhaps there is a better demo example from your end could explain this situation?

Thanks