Hi all,

I have a hardware question about data aquisition in FX3 design.

For example, I have an ADC which has two output: the ADC clock and parallel data which is synchronized to the clock. Since it is an external clock to CYUSB3014 chip, lets say the data rate is 100MS/s. How should I configure the CYUSB chip to read the data correctly?  The another way to ask this question is: how to make sure the sampling time of the CYUSB (using GPIF II) is synchronized to the external ADC clock.

If the ADC clock is fixed to be 104MHz, then if I use a divider to generate a 52MHz clock to be the CYUSB reference clock, in this way, will the data acquisition time automatically synchronized to the ADC clock?

Thank you.

 If you look at the GPIF designer tool, you have different options to configure it.

You can do one thing. Configure the GPIF as shown in the attached project. Configure GPIF as master so that it provides clock to the external device (ADC in your case). Select the communication type as Synchronous.

Go through the attached GPIF desinger project and the source code. This code is developed for AD9269 and it is not fully tested. But you can use it as reference to design GPIF descriptors for your application.

Thanks,

sai krishna.

 Attaching the FX3 soruce code

 Attaching the FX3 source code

 I am seeing some issue with attaching the projects. Please give me your mail ID. I will mail these projects to you.

Thanks,

sai krishna.

Thank you so much. It is very helpful.

I have one more question, at what frequency did you test your ADC + CYUSB3014? cause AD9629 has several sampling frequency options from 20 to 80MS/s. Actually my question relies in how clean is the clock generated directly by CYUSB3014. From my understanding, there is an onchip PLL to synthesize the system clock. In order to maintain the ADC performance, there is requirement on clock jitter, so do you have any measurement for the clock generated by the CYUSB chip, like, what is the phsae noise/ jitter look like @ highest frequency settings (say, 100MHz)?

Actually this is what I want to measure using the evaluation board, and based on the measurement I want to decide whether I should use CYUSB generated clock to sample the ADC or I have to make another indepedent clean clock for the ADC. For the latter option, I do face the synchronization problem.

Thanks.

Run

It was tested using ADC Eval board. Clock was taken out of board(ADC); input to FX3. As you can see in the firmware clock is configurable over SPI, We have tested 60Mhz max clock.

-dhanraj

You could bypass the FX3 SPI completely.  Program the clock GPIO pin to generate an interrupt on the appropriate edge.  Then, bit bang the data on the data pin using GPIOSetValue  This could be processor intensive, but I'm assumming you are not reading/writing to the ADC frequently.

Thanks dhanraj and dreitz, from my understanding, the clock of ADC and FX3 reference clock are independent, and data communication is in asynchronous mode. Is the above statement correct?

If so, I have another question. The FX3 reading speed from ADC depends on the ADC clock. There must be an internal clock of FX3 to transfer the data to the endpoint (or some buffer) ready for USB interface. So are there any requirement on the clock speed between ADC clock and FX internal clock such that the data can be read from ADC and transmitted to USB interface continuously, without data flow or any break point? Which document has related information upon this issue?

Thank again :)

No, it is synchronous. You can confirm from the example code(The example I have attached in previous post) and GPIF descriptor that FX3's PCLK is connected to ADC CLK pin. clock is input to FX3 from ADC. Clock output of ADC is programmable using SPI. since GPIF is configured to 32 bit, SPI is bit banged in the code.

I see. I agree with that the ADC output data is synchronized to the ADC clock which is set througn SPI from FX3.  So are the following statement correct:

(1) FX3 reading ADC data is triggered by the ADC clock. The reading speed is determined by ADC clock.

(2) ADC clock  can be independent from the FX system clock as long as it is less than 100MHz, and it can be generated from a seperate oscillator other than the FX3 reference.

Since I am design my own DAQ board, so i really need a confirm about this issue. Thanks a lot.

(1) FX3 reading ADC data is triggered by the ADC clock. The reading speed is determined by ADC clock.

[dbir]YES

(2) ADC clock  can be independent from the FX system clock as long as it is less than 100MHz, and it can be generated from a seperate oscillator other than the FX3 reference.

[dbir]YES

Great. Thanks a lot!!!!!!!!!!!!!!!