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SlaveFifoSync Mode,Flag A always be asserted when the data quantity is about 17MB/s
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SlaveFifoSync Mode,Flag A always be asserted when the data quantity is about 17MB/s

dadaqingwa posted on 20 Apr 2012 7:40 PM PST
Member
6 Forum Posts

 I use the FX3 in SlaveFifoSync Mode to transfer data from FPGA to PC. The PC End software is the "Streamer" Demo in SDK1.0.

I set the parameters as follow:

CY_U3P_DMA_TYPE_AUTO
Burst length = 0x0F; Buffer size = 16K; Buffer count = 8.


When the data send by FPGA is about 17MB/s,


I think the USB transfer speed is quickly enough, the Flag A(indicate buffer full) would not be asserted, but actually I found the Flag A is sometimes be asserted, It indicated the DMA buffer is full which it would be not! 

What are the possible reasons? Is that the "Streamer" read too slow？ But when I use the "Bulksourcesink" Demo to test the USB speed, It can reach 320MB/s.

Re: SlaveFifoSync Mode,Flag A always be asserted when the data quantity is about 17MB/s

aasi posted on 23 Apr 2012 01:35 AM PST
Cypress Employee
1073 Forum Posts

What is the duration of this full flag assertion?

The full flag is asserted during buffer switching as well. Are you configuring FX3 for many to one channel to work around this?

Regards,

Anand



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