Hi,

My question is respect to the timing diagrams provided in section 9.6 of the Cypress CY7C68013 FX2 datasheet.  Basically, for an internally sourced 48MHz IFCLK, are the numbers and picture with respect to IFCLK inside the device, or are they measured at the pin. 

The reason I'm asking is that probing at the output pins of the FX2 I see that for example that the CTLx output is actually driven several nanosections *before* the rising edge at the IFCLK pin.  IFCLK is not configured to be inverted and the number is no where near the spec'ed max clock to out of 6.7ns.  Same issue with the GPIF address and the data lines.

Can anyone provide any clarity? Thanks,

Raphael

 Hi Raphael,

If the IFCLK is not chosen to be inverted, both IFCLK (internal) and that appearing on external pin is the same. Can you please check IFCONFIG register and confirm it is not IFCONGIF.4 = 0 and IFCONFIG.5 = 1.

Do you mean to say, the timings being seen in the actuak pins are different fro what you specified using the GPIF Designer utility? Can you please attach the screenshot of the GPIF Designer utility showing the waveforms, and also that of actual waveforms from scope?

Regards,

Gayathri

 Hi Raphael,

Sorry for the typo.

Can you please check IFCONFIG register and confirm if IFCONGIF.4 = 0 and IFCONFIG.5 = 1.

Regards,

Gayathri

Hi Gayathri,

My question is not in regards to the actual GPIF waveforms.  They are correct as created from the GPIF designer.  My question is in regards to the AC timing diagrams in section 9.6 of the FX2 datasheet.  In that table are parameters Tsga, Txgd, and Txctl which are needed to create a proper timing budget for any external device connected to the GPIF.  When I actually measure the clock to out timing with IFCLK as an output, the outputs are 2-4 ns before the rising edge of IFCLK.  Unfortunately there are no minimum values in the table, so while this is possible, it is quite a ways from than the maximum values listed in the table.

I suppose it's not a huge issue since I'm just going to use the measured values, but if you were trying to design a board prior to having working silicon and you only had the datasheet, this could cause a headache for some.  I was just trying to understand why the outputs are advanced from the clock.

Regards,

Raphael

Hi,

You're looking at this based on one silicon that you've have in hand. Those values are based on our characterization of the worst case condition. The reason behind specifying the max here is this, that is the safe point after which you should be sampling.

Say you go with the values based on the silicon that you've have in hand. You might get units with timing value bigger than that in that case you might run into issues. Though the unit will meet all the datasheet parameters you'll still end up into issues due to timing. So for these parameters you should be designing based on the worst case.

Please let me know how you would use the minimum value in these cases.

Regards,

Anand

Hi Anand,

Thanks for the reply.  I would be interested in knowing what the min delay for the GPIF outputs are relative to the IFCLK.  With both the min and max values I can create proper contraints to meet setup and hold at the receiver.

Regards,

Raphael