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Strangely, I can CONTINUOUSLY get the data in the Slave FIFO , BUT I just fill the FIFO once with the external logic-FPGA.

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Strangely, I can CONTINUOUSLY get the data in the Slave FIFO , BUT I just fill the FIFO once with the external logic-FPGA.

	ainiludeer posted on 16 Mar 2012 5:07 AM PST Member 4 Forum Posts

Hi!

Here is a quite strange phenomenon which has been confusing me...

Things goes like this:

I feed the Slave FIFO with the external logic FPGA when a key is pressed.

Before the key is pressed down, FIFO_FULL_FLAG is high and FIFO_EMPTY_FLAG is low.

After the key is pressed, FIFO_FULL_FLAG is low and FIFO_EMPTY_FLAG is high. Obviously,it is normal.

However, when I access the data in the SLAVE FIFO through the control pannel, the FIFO_FULL_FLAG remains low and the FIFO_EMPTY_FLAG remains high. \

How can i fix it?

Re: Strangely, I can CONTINUOUSLY get the data in the Slave FIFO , BUT I just fill the FIFO once with the external logic-FPGA.

	Gayathri posted on 17 Mar 2012 12:01 PM PST Cypress Employee 428 Forum Posts

Hi,

Please post your code. I would like to take a look into the same.

Regards,

Gayathri

Re: Strangely, I can CONTINUOUSLY get the data in the Slave FIFO , BUT I just fill the FIFO once with the external logic-FPGA.

	PRJI posted on 17 Mar 2012 12:06 PM PST Cypress Employee 333 Forum Posts

Hi,

Please check your Endpoint buffer configuration whether its valid or not. For more information on valid endpoint configurations go through section 1.17 EZ USB endpoint Buffers of TRM.

Thanks

Prajith

Re: Strangely, I can CONTINUOUSLY get the data in the Slave FIFO , BUT I just fill the FIFO once with the external logic-FPGA.

	ainiludeer posted on 20 Mar 2012 04:57 AM PST Member 4 Forum Posts

I used the asynchronous mode. And the fequency of pusle clock of SLWR was too high.

It seems that there is liminition for the frequnency of SLWR...

Re: Strangely, I can CONTINUOUSLY get the data in the Slave FIFO , BUT I just fill the FIFO once with the external logic-FPGA.

	PRJI posted on 20 Mar 2012 07:44 AM PST Cypress Employee 333 Forum Posts

Hi,

Please see this http://www.cypress.com/?docID=33732.

Thanks

Prajith

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Strangely, I can CONTINUOUSLY get the data in the Slave FIFO , BUT I just fill the FIFO once with the external logic-FPGA.

Re: Strangely, I can CONTINUOUSLY get the data in the Slave FIFO , BUT I just fill the FIFO once with the external logic-FPGA.

Re: Strangely, I can CONTINUOUSLY get the data in the Slave FIFO , BUT I just fill the FIFO once with the external logic-FPGA.

Re: Strangely, I can CONTINUOUSLY get the data in the Slave FIFO , BUT I just fill the FIFO once with the external logic-FPGA.

Re: Strangely, I can CONTINUOUSLY get the data in the Slave FIFO , BUT I just fill the FIFO once with the external logic-FPGA.