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No PCLK
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No PCLK

dreitz posted on 15 Mar 2012 9:56 AM PST
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74 Forum Posts

We are using the GPIF II as a synchronous slave FIFO and the sample SlaveFifoSync software from Cypress .  We are not able to see PCLK coming from the chip.  Is PCLK free-running or only active during a data transfer? 

Re: No PCLK

dreitz posted on 15 Mar 2012 10:06 AM PST
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74 Forum Posts

Nevermind....seems I was misinformed about the direction of PCLK.  It's an input.

Re: No PCLK

dreitz posted on 15 Mar 2012 10:38 AM PST
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74 Forum Posts

How does one do this..."a clock signal can be generated by any GPIO pin by using Pulse or PWM mode of GPIOs"?  Any sample code available?

Re: No PCLK

dreitz posted on 15 Mar 2012 11:59 AM PST
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74 Forum Posts

Based on further research into the "complex GPIO", I will not be able to use GPIO23 and GPIO26 in PWM mode to generate a clock.  It also looks like I cannot use GPIO32 because of PMODE2.  Right?

Re: No PCLK

RobK posted on 19 Mar 2012 12:25 AM PST
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56 Forum Posts

Hi,

regarding PMOD-pin I found the following in the FX3's programmers manual:

"Pins [30-32] are used as PMODE [0-2] inputs during boot. After boot, these are available as
GPIOs."

 

Best Regards!

Re: No PCLK

lint posted on 19 Mar 2012 06:47 AM PST
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21 Forum Posts

" I was misinformed about the direction of PCLK.  It's an input." "it's an input" what do you mean? anybody tell me if I can select the PCLk direction without change any firmware parameter? 

Re: No PCLK

dreitz posted on 20 Mar 2012 10:14 AM PST
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74 Forum Posts

PCLK is always an input.

There is sample code in the latest SDK that deals with complex GPIO and supplying a clock from the PMW.  I don't think you can internally route it to PCLK.  Luckily, my PCLK is connected to an FPGA, we can supply the clock from there if we have to.



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