I use the FPGA + 32bit to send data to fx3.but always lost data from fx3 to PC,there is a Image about that at the bottom.

If I receive 512 Bytes from fx3 ,missing 4 word.when I get 1024 Bytes from fx3,it still lost 4 word.

I looked the fpga part,it works well.

so,help.

Is your FPGA code monitor the full flag to make sure it doesn't send data when the FIFO is full/busy?

Regards,

Anand

 YES,when the fifo is full,the flagB is to pull low,then I pull the wr in high state,so it will stop send data to fx3.

I think the problem is not in the fpga.because the data I recive from the fx3 is corect,the problem is lost four word

data.

If the problem in the fpga, I reviced the data with different size,the data could not be continuation .

It just lost four word.

Did you pay attantion to the flag latency of teh FX3? You have to use the partial full flag with watermark value for correct stopping data transfer on buffer full.

 oh ,I want ask you to help me,please tell me,which PC board are you using?

I want to buy a PC board with USB3.0.

the watermark? what is that?

 there is a 3 cycle latency between the buffer becoming full to the assertion of the flag.

Watermark is the used to counter this. Watermark is set to the assert the flag when there is space for x bytes in the buffer. So setting watermark to 3 for a synchronous interface would mean that the flag assertion happens when the buffer is full.

Regards,

Anand