i'm using the slave FIFO interface for bulk auto-in transfers directly from an FPGA to the host, in asynchronous mode.

Right after the FULL flag asserts, the FULL flag deasserts and the EMPTY flag asserts simultaneously.

I have attached a screen shot of the waveforms.

Any ideas of what could cause this?

 Hello Dan,

Flag pins (A,B,C,D) reflect the status of the Flags (EF, FF and PF) when data is in the peripheral domain (fifo). So as soon as the data comes into IN endpoint fro FPGA and is full, full flag (FLAG B in your case) gets asserted. Since it is in Auto mode, the data gets auto committed to the USB domain. Thus once the full data gets comitted t0 the USB domain, there is no more data in peripheral domain. Thus the full fllag (FLAG B) deasserts, and empty flag (FLAG C) asserts.

Regards,

Gayathri

Okay, that makes sense.

My driver guy seemed sure that he wasn't getting any data.

I'll put my USB analyzer to work...

On the USB side there is nothing but NAK.

Where could the data be going?

Turned out this was because we were reusing the fifoadr1 pin as gpio output PORTA.5 before using it in the slave fifo interface. Cypress was driving logic low while our fpga was driving logic high, resulting in .08V on the line. I set PORTA.5 to input before starting the slave fifo interface, and our fpga was able to drive fifoadr1 to 3.3V

although an unlikely scenario, it would be nice if this was errata'd.

Thanks!

 Hi,

Thank you for posting the issue here. We will look into it.

Regards,

Gayathri