Hi there,

I wanted to know when we use manual mode, the flagb&c dont work is it?  I am writing a test sequence from my master which is a PLD to the slave fifo (microcontroller cy7c68013a). I can see the test data in the endpoint buffer (of the slave) but the flags and byte counts always read empty! Has anyone come across this before?

Thanks in advance

Hi,

                Yes, all flags will work in manual mode. Go through 9.2.4 FIFO Flag Pins (FLAGA, FLAGB, FLAGC, FLAGD) section of TRM and double check your flag configuration.

 Thanks for the reply. The PF and empty flag trips but not the full flag. But thats not my concern now. What would be additional registers that needed to be set up for manual mode to work? I hve the epxconfigs, ifconfig,epxfifocfg,revctl, epxfifopfh&l,inpktend, fiforesets all set to appropriate values.  All i wanted is to see the sequence that i generated and sent to endpoint fifos in endpoint buffers. Cant think of anythng that could possibly go wrong because all the timings are right.

 Hi Poorni,

You can use the below sample code as reference, that configures FX2LP in Slave, Manual Mode:

void TD_Init( void )

{ // Called once at startup

  CPUCS = 0x12; // CLKSPD[1:0]=10, for 48MHz operation, output CLKOUT

  IFCONFIG = 0xCF; // for async? for sync?

  EP2CFG = 0xA2;     // EP2OUT, bulk, size 512, 2x buffered

  SYNCDELAY;           

  EP6CFG = 0xE2;     // EP6IN, bulk, size 512, 2x buffered

  SYNCDELAY;

  EP4CFG = 0x00;     // EP4 not valid

  SYNCDELAY;               

  EP8CFG = 0x00;     // EP8 not valid

  SYNCDELAY;

  FIFORESET = 0x80;  // set NAKALL bit to NAK all transfers from host

  SYNCDELAY;

  FIFORESET = 0x02;  // reset EP2 FIFO

  SYNCDELAY;

  FIFORESET = 0x06;  // reset EP6 FIFO

  SYNCDELAY;

  FIFORESET = 0x04;  // reset EP6 FIFO

  SYNCDELAY;

  FIFORESET = 0x08;  // reset EP6 FIFO

  SYNCDELAY;

  FIFORESET = 0x00;  // clear NAKALL bit to resume normal operation

  SYNCDELAY;

  EP2FIFOCFG = 0x00; //manual mode, 8 bit mode

  SYNCDELAY;

  EP6FIFOCFG = 0x00; //manual mode, 8 bit mode.

  SYNCDELAY; 

  OUTPKTEND =0x82;   //arming the EP2 OUT endpoint twice, as it's double buffered.

  SYNCDELAY;

  OUTPKTEND = 0x82;

  SYNCDELAY; 

  SYNCDELAY;

  PINFLAGSAB = 0xE0; // FLAGA - indexed, FLAGB - EP6FF

  SYNCDELAY;

  PINFLAGSCD = 0x08; // FLAGC - EP2EF, FLAGD - indexed

  SYNCDELAY; 

}

Regards,

Gayathri

 Thanks Gayathri..That was helpful...I am using only IN direction for no. If I have to skip a packet what really happens?  Say I have data flow continously.. Putting the skip bit to one I should skip 512 bytes (in my case) of the data right? and see the remaining data on the endpoint buffer?

 Hi again,

Question is about figure 5 endpoint configuration. I was trying IN EP4 and got it to work with e613 set to E0 . That means its quad buffered selection... But EP4 and EP8 only work as double buffer.. How did this config work then? I was trying the same with EP2 and it would not work. In fig 5 if I m using option 1 say but just need EP2, do I still have to enable ep4,6,8 and use my selection pins for selecting ep2? like ifconfig 00->ep2, 01->ep4 and so on...

Summary -  Can i do an IN EP2 only with 512 double/quad buffer?

 Hi Poorni,

Regarding Skipping of an IN packet: You were right. By writing to the INPKTEND register, with the endpoint number and skip bet set to 1, will skip the packet from the IN endpoint. If the packet size is set as 512, it will skip one packet (512 Bytes sized).

Now in your next response, I did not get which is the figure that you were referring to. Please clarify.

I think, you got confused with EP4CFG and EP2CFG. In EP4CFG, EP4CFG[0:3] are by default zero, and cannot be modified. They are read only bits, since EP4 will always be double buffered. EP4CFG[0:1] does not represent the buffering, like in EP2CFG and EP6CFG.

Also I did not clearly understand the remaing part of your question as well.

Regards,

Gayathri