I am using the CY4684 development board and have an external FPGA reading the data from the USB chip as the external FIFO master. I am using EP2 in an AUTOOUT configuration. I can successfully transfer two complete 512 byte packets through the USB chip, then the USB chip will no longer accept any more data. When it is in this state, the slave FIFO is empty (EP2FIFOBCH/L is equal to 0), yet EP2CS is equal to 0x10, indicating that it has one packet in it.

Whenthe system starts, NPAK is 0x04, and EP2FIFOBCH/L is equal to 0. 

I send one packet, NPAK is 0x10, and EP2FIFOBCH/L is equal to 0x0200. 

I send a second packet, NPAK is 0x28, and EP2FIFOBCH/L is equal to 0x0400.

I then read one packet from the FPGA, NPAK is 0x10, and EP2FIFOBCH/L is equal to 0x0200. 

I then read one packet from the FPGA, NPAK is 0x10, and EP2FIFOBCH/L is equal to 0x0000. 

Are you using a valid FIFO configuration? Invalid FIFO configuration might cause this kind of behavior.

Please look into section 1.17 EZ-USB Endpoint Buffers -page 30 of TRM for valid fifo configurations. 

Regards,

Anand