hi:

How to test"Cypress\FX3 SDK\firmware\slavefifo\slfifosync"

FPGA and FX3 link below:

SLCS# --GND   SLWR# --GND   SLOE# --HIGH   SLRD#--HIGH   PKTEND--HIGH     A1 --GND       A0 --GND

PCLK---48MHZ   D0/D15--DATA

The tools with "CyControl.exe" test error.Error message:"BULK OUT transfer failed with Error Code:997"

Since you're talking about Bulk OUT I assume you're trying to do slavefifo read. Please refer the datasheet for the timing diagram. Looking at your pin signalling description seems you've set it up for FIFO write.

Regards,

Anand

Also I can see a few BULK OUT transfers before you run into the code 997 (which is overlapped I/O pending) so it seems FX3 is up.

Regards,

Anand

Thank you!

Information from Cypress Tech Support team I got days before:

When you using slave fifo, nSLOE, nSLRD, nSLWR CAN NOT be ALWAYS LOW. It can be low only when there is buffer/data can be accessed. Otherwise DMA may meet problem.

That means, if you are doing fifo reading, nSLOE = nSLRD = 0 can ONLY happens when Flag Pin is High which means there is data can be read. Otherwise, the pin should keeps 'b1. Tie 0 them to 0 is not an option.

Data packet sent from PC is used to filling your internal DMA buffers.