Hi,

We are designing FPGA to write data to FX3 Synchronous Slave FIFO. Our FPGA use thread 0 (A0,A1 = 00) and monitor FLAGB pin for FIFO full status. For firmware we use SlaveFifoSync example provided in SDK.

In application note AN65974[Designing with the EZ-USB FX3 Slave FIFO Interface], it mention that there are two-cycle latency incurred in current thread flag.

So we try to configure the FLAGB as dedicated thread flag for thread 0. What we modified is to change

{CY_U3P_PIB_GPIF_CTRL_BUS_SELECT_ADDRESS(5)      , 0x00000018}, // FLAGB as the  current thread  flag

as

{CY_U3P_PIB_GPIF_CTRL_BUS_SELECT_ADDRESS(5)      , 0x00000010}, // FLAGB as the  dedicated thread 0 flag

However, the two cycle latency are still exist after we apply this patch...

Is there any solution available to configure full flag without the latency?

Regards,

Elvis

The app note does mention a  workaround for this using watermark in the partial flag section. Have you tried this?

Regards,

Anand

Hi,

We are trying to modify CY_U3P_PIB_GPIF_CTRL_BUS_SELECT_ADDRESS(5) as partial flag for thread 0. And use CyU3PGpifSocketConfigure() to configure the watermark value. However we don't know how to specify parameters for CyU3PGpifSocketConfigure(), such as threadIndex, socketNum, and burst.

 Are there any examples that show how to configure the partial flag with watermark value?

Just wanted to chime in to say that we see a 3 cycle delay on both the full flag and the partial full.

We can compensate for the delay by lowering the watermark 3 samples, but it's a clunky solution.

Hi dschneider,

We also see 3 cycle delay on full flag. However we still don't know how to configure the watermark.

Would you mind to post your solution that lowers the watermark 3 samples here?

Regards,

Elvis