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Which IO standard (LVTTL/LVCMOS/3.3/3.0/2.5) to choose when connecting an FPGA with FX2LP? Both are powered at 3.3V
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Which IO standard (LVTTL/LVCMOS/3.3/3.0/2.5) to choose when connecting an FPGA with FX2LP? Both are powered at 3.3V

David8888 posted on 25 Oct 2011 3:37 AM PST
Senior Member
15 Forum Posts

I am connecting a Cyclone III FPGA directly with FX2LP, but I am not sure which IO standard to choose on the FPGA side?  The options in Altera Quartus II are: LVTTL-3.3V, LVCMOS-3.3V,  LVTTL-3.0V, LVCMOS-3.0V, 2.5V, etc.. The IO banks of the FPGA are powered at 3.3V using the same power source as the FX2LP.

I have a FPGA program which seems to run correctly using the default 2.5V IO Standard. However, if I change the IO standard to LVCMOS-3.3V or LVTTL-3.3V (which should be the correct choice),  the program does not seem to work.

Thanks for any suggestion in advance.




Re: Which IO standard (LVTTL/LVCMOS/3.3/3.0/2.5) to choose when connecting an FPGA with FX2LP? Both are powered at 3.3V

aasi posted on 25 Oct 2011 10:47 AM PST
Cypress Employee
1090 Forum Posts

 If the IO standard you chose meets the VOH, VOL, VIH and VIL specification of FX2LP then it should work fine. You should be able to look this up in the FPGA datasheet did you check this out?

What is the failure pattern you're seeing when you use the 3.3V IO standards? Does the LVTTL need external pull-up?

Regards,

Anand



Re: Which IO standard (LVTTL/LVCMOS/3.3/3.0/2.5) to choose when connecting an FPGA with FX2LP? Both are powered at 3.3V

David8888 posted on 26 Oct 2011 09:16 AM PST
Senior Member
15 Forum Posts

Thanks Anand. After checking the FPGA's Voh, Vol, Vih, Vil, it looks that the LVTTL 3.3, LVTTL3.0, LVCMOS3.3, LVCMOS3.0, LV2.5 are all compatible with FX2LP.  By reading the Cyclone III's manual again, it looks like the selection of IO standard in Quartus II is actually meant to select the current strength rather than voltage. The IO voltage has already been determined by the hardware anyway. Thus it should not be selectable in the software. Therefore I check the FPGA program again and find the there is one input fed by FX2LP has a more than 400 fan-outs, but FX2LP's Iout is only about 4mA. After reducing the fan-out of that pin, the program seems to be working fine under all IO standard options.  






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