I cannot get the 32 bit sync slave FIFO working. In 16 bit mode the firmware works well and transfers 120MB/s to the host with 16 packets per burst. But the 32 bit mode don´t work, no data is transferred and the CyFxSlFifoPtoUDmaCallback() is never called HW-breakpoint using J-Link debugger). I use a simplest hardware connection: A 100Mhz oscillator on PCLK. WR, CS, A0 and A1 pulled to low; OE, RD, and PKTEND pulled to high. But only the 16 bit mode works.
How can I get this working? I use the beta 3 SDK. In the slave fifo appnote a cannot find a difference between 32 bit and 16 bit mode regarding the control lines.

We did test this firmware before sending it out... Let me check with our team on this again...

Please cofirm that you aren't changing anything in the hardware environment (i mean the wiring of WR, OE etc) between 16-bit and 32-bit firmware when you do the testing.

Regards,

Anand

There is no change in hardware, the connection is hard-wired on the FX3 Dev Kit. The source is fresh installed with Beta 3 of SDK.

Hi,

I was able to get 32 bit mode working whenever PCLK was 50MHz or 75 MHz but at 100MHz the slave fifo firmware won't work. Another thing I noticed was I had to change the DMA channel to auto before I could get the data rate up to 90MBs - I only have a gen1 PCI slot for the USB 3 card. In other words I couldn't use the CyFxSlFifoPtoUDmaCallback() as it slowed everything down.

Sodafarl

Oh, thank you for your message. I will try to solder a slower oscillator on the board. Maybe it works after this. At the moment 100MHz is mounted.

Hi Chris,

I'm still working on this. I've asked our software team to retest this firmware. I'll update the thread once I have a update from our side.

Regards,

Anand

Hi Chris,

2 things I wanted to check on this

1. Are you using burst mode or non-burst mode transfer? If you're using burst mode what is the size of burst you're using?

2. Which revision of the DVK are you using?

Regards,

Anand

Hi,

1. As I wrote, I use "continous" transfer as the #WR is pulled low and I do not look at the fifo flags. Did you mean this with burst transfer? Or did you mean the packets per burst transfer? In this case, I tested with 1, 4, 8, or 16 packets per burst, changing the descriptor, the endpoint init and the dma size. Nothing works with 32 Bit mode, but all work with 16 bit mode.

2. I use the REV 2 of the FX3 DVK Device Board. The FX3 is labeled with

-BZXIES
1113 8
619245

Just a few minutes after my post, the hardware modification was done and now there is a 40MHz source for PCLK. And now the 32 Bit mode works. Only with 120MB/s but it works for now...

Hi,

I increased PCLK to 95MHz and 32 bit mode slave fifo firmware works. I tested the bandwidth on a Dell T5500 with USB3 controller card. I got 125MBs. This is a lot less than it should be and I don't think the problem is with the computer set up, drivers or controller card.

Sodafarl

I tested again with 80MHz PCLK and ist works also. The speed is 160MB/s at my HP DC6000 with NEC PCIe Controller and Windows 7 x64. With WinUSB the speed is similar. I set up the DMA channels to Auto Mode. With Manual Mode there was only 120MB/s.

It seems to be a issue due to the internal clock configuration done by the firmware when we use a 19.2MHz clock source.

With 26MHz clock even the current firmware will work at 100MHz. The next version of the SDK will have this fix implemented so that irrespective of the clock source used you should be able to work at 100MHz.

Regards,

Anand

 Is this similarily an issue when using a 19.2KHz crystal?

Thanks!

 The 19.2MHz, 26MHz I'm speaking about is the crystal/oscillator used for FX3.

Please let me know which similar issue are you talking about?

Regards,

Anand

 Sorry, I was asking if the issue in this thread exists when using the crystal as well as the clock input, which it seems it does.

Yep. if the crystal/clock source is 19.2MHz. Just a small bug in the current firmware.

When will the next fimrware be released?

Thanks,

lumpi