Hi, I’m trying to use your  slave fifo GPIF firmware demo for streaming data from an FPGA to a host PC.
At a first attempt I’m only interested on measuring the maximum device to host transfer bandwidth.

We used the GPIF designer to configure the GPIF interface for synchronous slave fifo with a 32 bit dada bus width.

On the FPGA we set (fixed):
SLOE set to 1  // no GPIF read
SLCS set to 0  // GPIF is always selected
SLWR set to 0 // continuous write
SLRD set to 1  // no read
PKEND set to 1 // only 1024 byte packets
ADRESS set 00 // only thread 0

We verified that the above listed signals have the correct logical value on the FX3 pins and we would expect to measure the maximum (device to host) transfer bandwidth using your sinch. Slave fifo example together with your streaming application… but… nothing happens. After a first short period where flagA is reporting “FIFO not full” once it get FULL it simply stops. It seems that CyFxSlFifoPtoUDmaCallback is newer called to forward the data to EP1 as we would expect.

Any suggestion about this?
Considering the value of the signals of interest presented above, would you expect your synchronus slave fifo example to work correctly?

Thanks in advance

Athos

Hi, I've exactly the same problem. I’m controlling the GPIF interface by means of an FPGA. As a first attempt I used the SynchronousSlaveFifo stuff provided by Cypress with just CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT set to one in order to enable the 32 bit interface.

If I correctly understood the documentation and the comments in the code, to stream data from the device to the host in the SynchronousSlaveFifo firmware I have just to set:

Addr[0,1] to 0 in order to permanently select thread 0 (device to PC stream) and

SLCS : ‘0’

SLWR: ‘0’

SLRD:’1’

SLOE:’1’

PKTEND: ‘1’  (no short packets!)

With the above configuration (I know that neglecting flaga/b I’ll lose some data when fifos are full, but at the moment I don’t care about this, I just want to see the example working ) when I run the Streamer application provided by Cypress and I connect it to the In endpoint I would expect that data is streamed form device to the host.

Unfortunately this doesn’t happen. I only get USB read timeouts.

All the signals have the correct value on the FX3 including th PCLK (verified with an oscilloscope).

Are the above statement correct ?

Does anyone had success on using the SynchronousSlaveFIFO example as is ?

Do I missed something on how I’m handling the FX3 signals ?

Thanks in advance, Joel

Sorry I did a mistake... things are working now...

Joel

Which data transfer rates can you achieve using the 32 bit slave fifo. Does the slave fifo work correctly with multiple packetes per burst?

Joel,

What was the mistake that you did and how it is working now.

Could you please share with us.

Thanks,

sai krishna.