I am using 68013A's 16-bit Slave FIFO to communicate with an FPGA. I have two continous data stream between the PC and the FPGA via 68013A. EP2 is configured as quad buffered BULK OUT, and EP6 is configured as quad buffered BULK IN. To share the use of the FIFO's data bus, I will need to switch the FIFO ADDR between EP2 and EP6 constantly, can I switch the FIFO ADDR from EP6 (BULK IN) to EP2 (BULK OUT) regardless of whether the data in EP6 have been committed or not?    

If you try to access the endpoint which is empty then you won't get anything on the bus. In case you're are not implementing flow control then if the endpoint buffer gets filled in the middle of your access cycle. Then you're going to partially read data from FX2LP which will make you lose sync.

Why would you want to do something like this?

Regards,

Anand

Thanks Anand. I have two threads on PC side, one thread acquires data from EP6 continously, each time acquires 20000 Bytes using asynchronous data transfer (Begin/Wait/Finish). The other thread output data to EP2 continously, each time outputs 20000 Bytes using asynchronous data transfer (Begin/Wait/Finish). On the FPGA side, there are two double-buffered data buffers, the one for data acquisition (EP6) has 20000 x2 bytes, the one for data output (EP2) has only 1024 x 2 bytes. Both data buffers are clocked to input / output at certain sampling rates.  The problem is that I cannot wait for EP6 to complete 20000-Byte transfer before switching to EP2, otherwise the continous output stream will be interrupted because the buffer size for EP2 is much smaller than the buffer size for EP6. Therefore I want to design a controller in FPGA which allocates time slots (say 1000 ifclk cycles) to the input stream and output stream without checking whether the data in EP6 has been committed or not, and the data in EP2 has been read or not. I guess the input/output stream will recover seamlessly after the it gets the time slot again.