Hello,

I'm working witt CY7C68013A. It is transfer 2MB data to host.
EP6 is used as input endpoint.

In flow state, I've set as below.
DataXFER : Rising edge
Master strobe half period : 2
Flow logic : if(FIFOflag=1 and FifoFlag=1)
               then CTL0 = 1;
      else CTL0 = 0;
  
problem is

With Logic analyzer, I've counted CTL0 pin's signal.
It's last counting number is 1023999, not 1024000.

In host program , WaitForXfer() is return correctly within about 125msec.
in my think, 125msec is correct consumed time to transfer 2MB.
 

Ant the FinishDataXfer's inLen after function return  is 1024000.

1. Why does Physical counting is differ to others?

2. Our memory will output data on falling edge of CTL0,
then MCU will get data on rising edge.
is it correct?

3. in my test, bulk speed for Read is 16MB/sec . but on other documents,
 their circuit has about 40MB/sec.
 I've attached working file.

viod host_read_code(){
...................

  
  inlen=1024000*2;

  SendCmd(VX_B3);//set GPIFTCBx as 1024000(0x0F_A000) and trigger GPIF

  UCHAR  *inContext = InEndpt->BeginDataXfer(inData,inlen,&inOvLap);
  
  InEndpt->WaitForXfer(&inOvLap,10000);
  
  
  success = InEndpt->FinishDataXfer(inData,inlen, &inOvLap,inContext);

  SendCmd(VX_B4);//vendor cmd. stop upload.

...................
}

//Below is MCU code.
BOOL DR_VendorCmnd(void){

..............

case VX_B3: // enable IN transfers
 {
  
  *EP0BUF = VX_B3;
    EP0BCH = 0;
  EP0BCL = 1;
  EP0CS |= bmHSNAK;

  SYNCDELAY;
  FIFORESET = 0x06;  // reset EP6 FIFO

//=====================================

  SYNCDELAY;
  GPIFTCB3 = 0x00;
  SYNCDELAY;
      GPIFTCB2 = 0x0F;
  SYNCDELAY;
      GPIFTCB1 = 0xA0;
        SYNCDELAY;
        GPIFTCB0 = 0x00;
        SYNCDELAY;
   
  Setup_FLOWSTATE_Read();
    
        SYNCDELAY;
  //read transaction & ep 6.
        GPIFTRIG = GPIFTRIGRD | GPIF_EP6; // launch GPIF FIFO READ Transaction to EP6 FIFO
      SYNCDELAY;

 
   break;
    }

 Hi,

As I went through your firmware, I noticed that you had a value of 0x3E into FLOWLOGIC register. According to what you said, to make the logic as if(FIFOflag=1 and FifoFlag=1) , you have to assign it as 0x36. I just wanted to bring this into your notice first.

Then about the question:  Our memory will output data on falling edge of CTL0, then MCU will get data on rising edge.
is it correct? : As long as the timing of ext FIFO and the FX2LP is met, there is nothing to worry about keeping it so.

Regards,

Gayathri

 Hi,

Do you mean to say that the actual number of bytes transferred is correct (i.e 1024000 words, same as the value returned by FinishXferData function) and that the only in the logic analyzer, it shows up as different? Or do you mean to say that there is 1Byte missing in the original data transferred?

As you said, I have also seen upto ~40MB/s throughput with FX2LP. Did you use the Scremer/Streamer application that comes with Cypress Suite USB for checking the same? If not can you please check with same and let me know the result.

Regards,

Gayathri