I am al litte confused regardig the flags and their connection to the threads of the FX3. In the slave FIFO example the FLAG B is a copy of FLAG A and the flag is connected to the current thread. Its not clear to me if there are two threads (one for P to U and one for U to P) or only one thread (the software thread SlFifoAppThread_Entry).

Is it possible to use the FIFO flags like the FX2 controller? I want to use one flag fixed to the OUT endpoint (as empty flag) and one flag fixed to the IN endpoint (as full flag)? In the firmware example I cannot find the connection between the dma channels and the threads (0 to 3). Can you explain it to me? Thanks a lot.

Christian

Hi Chris,

Please look at the slave FIFO app note. It has a section where it clearly explains the FLAG configurations possible. This should help you understand the thread and possible FLAG configurations.

Regards,

Anand

Thanks for your answer. I´ve read the Application note, but this one is not really clear to me: "The sockets that are to be used
must be mapped to a thread. This mapping is done by EZUSB FX3 firmware".
I did not found the mapping of sockets to four possible threads in the example firmware. Maybe I dont understand this correctly...
The flags configuraion is clear, but not the mapping between the FIFOs and threads....

No further tips for me? What are the A1:A0 adresses of the current_thread using in the slave fifo example firmware? In the firmware I can find this mapping:

/* Used on FX3 silicon. */
#define CY_FX_EP_PRODUCER_PPORT_SOCKET    CY_U3P_PIB_SOCKET_0    /* P-port Socket 0 is producer */
#define CY_FX_EP_CONSUMER_PPORT_SOCKET    CY_U3P_PIB_SOCKET_3    /* P-port Socket 3 is consumer */

But I think this is for the DMA controller only? Where can I find the socket to thread mapping?

After crawling a night long in the header files with hundreds of registers I think I found the solution: The 4 registers CY_U3P_PIB_GPIF_THREAD_CONFIG_ADDRESS map one of the 32 PIB sockets to the 4 physical threads of the GPIF. This is coded in the 5 least significant bits. So the SyncSlaveFIFO firmware example uses thread 0 and 3, as the 4 threads are mapped to the PIB sockets 0 to 3.

Is this right? I thik this mapping is not completely explained in the slave fifo appnote.

0 and 3 are the (address pins or sockets) and 0 pin is to send data in to the usb to pc and when u are connected to the socket 3 u can read data out from the usb. so far I could understand this but later can I connect an other socket (consumer)out from the same thread ???

Or should I create an other thread for it

Hi Chris,

You are right.

The word “thread” refers to a hardware thread (FX3 terminology), not a software thread.
Let me explain a little bit more on the term “thread” in case of FX3.

Basically we have 32 sockets on the GPIF port of FX3. Socket will be having some buffer attached to it and each socket (numbered 0, 1 ,2 ,3) are mapped to the thread 0, 1, 2, and 3.

Thanks,

sai krishna.

Hello Sai Krishna,

I have 3 questions

1 .SO you mean to say that the address signals are meant to address the threads but not the sockets and the sockets are configured using dma channel configuration is it right??

2. What about the remaining other sockets other than (0,1,2,3) are all sockets connected to the 4 threads ??

3. This is regarding the Flags. Do the flags provide the status of the endpoint buffers??

Please clear these points

regards,

Pruthvi Raj 

Hi Raj,

Please find answers to your questions below:

1 .SO you mean to say that the address signals are meant to address the threads but not the sockets and the sockets are configured using dma channel configuration is it right??

Actually address lines addresses the sockets not treads. Sockets are mapped to threads. Socket 0 is mapped to thread 0.

Socket 1 is mapped to thread 1

Socket 2 is mapped to thread 2

Socket 3 is mapped to thread 3. This is a default mapping. Again if you want to access socket 4 then it is mapped to thread 0. socket 5 is to thread 1 and so on.

For more details on 2bit addressing (to address first 4 sockets) and 5bit addressing (to access all 32 sockets), please refer to the following application notes:

http://www.cypress.com/?docID=39757

http://www.cypress.com/?docID=34371

2. What about the remaining other sockets other than (0,1,2,3) are all sockets connected to the 4 threads ??

http://www.cypress.com/?docID=34371

This talks about addressing all 32 sockets

3. This is regarding the Flags. Do the flags provide the status of the endpoint buffers??

when you create a DMA channel between USB endpoint and a P-port side (GPIF II) socket then flags indicate the status of the buffer allocated for the DMA channel based on which side is producer and consumer.

Thanks,

sai krishna.