Hi,

I've got a question concerning the "Synchronous Slave FIFO interface with 32-bit data bus". It’s the interface between the FX3 and a FPGA in our application.  I’m wondering what happens if the USB packet length is not a multiple of 4 that means it fits not completely to the 32 bit bus width.
During the read sequence (from FX3 to FPGA) the last 32-bit-word that is read from the FX3-FIFO will contain less than 4 bytes. Therefore the FPGA doesn't know which bytes of the last word are valid. On the other hand during the write sequence (from FPGA to FX3) the last 32-bit-word that is written to the FX3-FIFO will contain less than 4 bytes. In that case the FX3 doesn't know which bytes are valid. I think there must be a kind of “byte qualifier” signal to mark the valid bytes within the 32-bit-words. Is it possible to configure some flags in the GPIF II as “byte enable”? I didn't find any hint in the application notes.

Best regards...

Hi,

We don't have a way of qualifying the data if the size of the last transaction is smaller than the bus width.

Since the requirement and the packet sizes that will be sent are known based on the end design it is up to you to implement a logic by which both sides sync up i.e. pad the data, send the byte count as part of the packet etc.

Regards,

Anand

Hi,

OK, I see. So we' have to insert some stuff bytes at the end of the packet if necessary and analyze the packet length in the protocol header.

Thank you for your quick reply!

Best regards...