Hi

i'm searcing for FPGA configuring example in SuiteUsb 3.4.5 installation, but i cannot find the software FPGA configuration utilities and all code and firmware about this example

Someone can helpme?

Maybe have i  to use another revision of SuiteUsb.

Thanks in advance

Please look at http://www.cypress.com/?rID=46029.

Regards,

Anand

Thanks Anand

You are always on time and accurately.

Best Regards

 Hi aasi,

It seems that the page you suggestted isn't available now.

Could you please give me some examples on FPGA configuration using FX2..?

Thanks.

BR/Lucev

It is one of our application note on how to configure Spartan using FX2LP. It has been pulled down for internal review. Please let me know your mail id I'll send across a beta version of the app note.

Regards,

Anand

 Hi anand,

Thank you for your help.

My e-mail address is (  lucev.wang@gmail.com )  and please send me that app note.

In my design, I wanna use FX2LP to configure an Altera FPGA(GPIF func) and then to transfer data between PC and FPGA(SlaveFIFO func). Do you have examples or suggestions for FX2 uses like this?

Thank you again and sorry for I made a mistake of your name last time.

Best Regards / Lucev,

                   lucev.wang@gmail.com

 Hi,

http://www.cypress.com/?rID=43046 should help you with the 2nd part. I'll mail the beta version of configuring FPGA app note in a few mins.

Regards,

Anand

 Hi Anand,

I have read http://www.cypress.com/?rID=43046 and thank you very much.

My 1st question is-- how to use the same FX2 to do both parts( first func as GPIF and then SlaveFIFO )?Do I need two different FWs( init to GPIF and to SlaveFIFO ) and re-program FX2 with FW2 after configure FPGA with FW1?

My 2nd question is ,in GPIF mode, can a FPGA config status pin be connected to a FX2( 56pins )'s I/O like PA0,not its RDY pins?Because in SlaveFIFO mode,two FPGA IOs are connected to RDY0&RDY1.If the FPGA config status pin is connected to RDY,it means a FPGA IO is connected to FPGA config status pin.FPGA will probably not work correctly.

Thank you for your patience.You are really a nice engineer.

Best Regards/Lucev

 Sorry Anand,

I checked my gmail just now and didn't found mail from you. Did my mail box not func well?

You can mail to another mail address( lucev@qq.com ).

Thank you and good luck.

BR/Lucev. 

The gmail id didn't work. Sent to the other id. The configuration firmware does not use RDY pins. If you're using auto mode then slave FIFO firmware should be simple. Please look at the configuration app note as well and then update here in case of any queries.

Regards,

Anand

  OK,I‘ll read the app note and have a try.

Thank you for your support, Anand. Have a nice day!

BR/Lucev

You might find FPGALink useful. It is an open-source cross-platform library that:

• Loads custom firmware into the FX2LP using libfx2loader.
• JTAG-programs a Xilinx FPGA.
• Subsequently communicates with a supplied VHDL reference design using FX2LP slave FIFOs.

It supports many of the Digilent FPGA boards natively (e.g Nexys2, Nexys3, Atlys), but there's also an FX2LP reference design if you want to make your own PCB.

- Chris

Can you please send me the new copy of this example file and documentation.

In previous pdf i find two problems

1. PE0 and PE5 pins are used these pins are not available in 56 pin package. 

2. Its is recommended that you can use 56 pin package.

3. We need to modify the code to some other port to get this working.

Kindly reply.

Thanks and Reards

Amol

My email address is amolshet@ti.com

Hi,

Please create a tech support case (MyAccount -> MyCases) to receive a copy of the same.

Regards,

Anand

Hello Anand,

I think few dought are resolved like the pin connection and other thing from GPIF software but I am unable to find the FPGA configration utility. Sorry I am new to this device and may take some more time to ramp up.

Thanks and Reagrds

Amol

 Hi,

       Find the attached.

Thanks

Prajith