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CY7C68000 UTMI 16 bit data bus, signals error. Help !
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CY7C68000 UTMI 16 bit data bus, signals error. Help !

Li2011 posted on 09 Aug 2011 12:04 AM PST
Member
2 Forum Posts
I am debuging my USB system. It is 3C80 FPGA + CY7C68000 USB PHY. The problem is that USB communication don't stable. It is OK in first several seconds, then disconnect with USB Host. Capturing 2 photo of the UTMI signals as follow. Picture 1 & 2, Channel 4 is 30MHz PHY CLK. Channel 3 is RxValid. There is difference clock to control out time on RxValid. One is about 5ns, another about 12ns. And there is a ~10ns low pulse on RxValid of picture 2. I think it's the point of my problem in picture 2. I try to find out why RxValid so strange, but fail. Any suggest to debug my USB connect?


Re: CY7C68000 UTMI 16 bit data bus, signals error. Help !

Li2011 posted on 09 Aug 2011 12:06 AM PST
Member
2 Forum Posts
piture 2

Re: CY7C68000 UTMI 16 bit data bus, signals error. Help !

aasi posted on 12 Aug 2011 08:54 PM PST
Cypress Employee
1090 Forum Posts

The capture is not clean to figure to compare timing and find out what operation is being done on the bus. Do you have a cleaner capture?

Have you tried hooking up a CATC to see what is the behavior seen on the USB bus so that you can isolate the signals that you should be probing?

Regards,

Anand






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