I am looking at converting my USB2 solution to this chip for my next design.  I have a general question.  With this new solution, if I want to a Async/Sync Write what types of USB traffic is required?  Today I do a Control transaction to setup the addresses and then a bulk transaction to do the data transaction.

Could someone describe, using the current FW and PC Software driver supplied by Cypress, what USB packets are required to do the following.

1) A simple 32 Bit Write

2) A Simple 32 Bit Read

3) A 64K Byte Write

4)A 64K Byte Read

What type of USB Transaction Control, Interrupt or Bulk and what are the contents of the packets?

Ken

The type of endpoint to be used depends on one's end requirement. Is guaranteed bandwidth a must for your design?

Regards,

Anand

In my current model with the previous FX, I have the GPIF bus connected to a memory port where I can do single word accesses or  large 51k or larger block addresses.  I currently send out the address/data on a control transactioin which sets up the GPIF address DMA and the GPIF  bus and I do a series of bulk transaction for the data.

When i look at the data sheet for the USB 3 device, Async transaction, the bus will send out an address and then data on the following strobes.  How does the current FW setup the address portion of the transaction.  For now lets assume that I am doing a large 512K USB Out transaction with multiple out packets.

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A better description of what I am after.  In the current FW example SDK which I have not looked at.  If I want to send out a large amount of data to a specific address on the GPIF bus, does the FW expect two USB transactions.  One control sequence to actually initialize the address portion of the GPIF bus and then bulk transaction which would DMA the data to/from the USB/DMA <-->GPIF bus?

I am not looking for BW analysis as there are two many variables that can interact with this.  I am looking at specific USB seqeunces for the examples in the SDK.