When I clocked the FX2LP 16-bit Slave FIFO Auto In at 48MHz, I always got some data errors, i.e. the data received from the FIFO on the host PC side were a bit different from the data sent to the FIFO on the FIFO master side. The problem can be resolved by changing the FIFO clock to 30MHz. I noticed that 16-bit Slave FIFO clocked at 30MHz means a data transfer rate of 480 Mbit/second. So my question is, does FX2LP supports 16-bit Salve FIFO with 48MHz clock? or maybe 48Mhz clock should only be used for 8-bit Slave FIFO?  I ask the question because I  want to know whether the issue is caused by my PCB design or not.

Yep. It can support 16-bit mode at 48MHz also. Do you see a pattern in the data corruption or is it random?

Regards,

Anand

There was a pattern there, but not fully repeatable. I have three prototypes with the same PCB design. Their problems are the same.

It is quite possibly a timing issue or your clock isn't clean. Do you happen to have a logic analyzer to analyze the timing and see if all the timing parameters are being met??

Regards,

Anand

At 48MHz the setup and hold timing of the FX2 is very hard to handle. You can run at 30MHz or slower. the maximum achievable real data rate to the PC is about 40MB/s, so you can reach this with at least 20MHz IFCLK.

I had the same problems running at 48MHz, so I use now 40MHz or even 20MHz external IFCLK and this is stable, no words are missing or wrong. And the overall speed is nearly 40MB/s.

Thanks a lot. I did not using any logic analyzer to check the timing. But I agree there should be some timing problem there. I think I can live with 30MHZ IFCLK for the time being.