Hi,

my question is related to synchronous slave FIFO interface which I want to convert to AXI4-Stream interface.

The documents used are:
[1] CYUSB3014
[2] AN65974

The direction in question is from an external device to EZ-USB FX3 chip (writing).

1. Is possible to assert SLWR simultaneously with SLCS (with ADDR and DATA IN loaded), or is it necessary to assert SLCS at least one cycle before asserting SLWR? In the state transition diagram in the GPIF II Designer there ate two transtions (from IDLE to ADDR and from ADDR to WRITE).

2. When ADDR is set and SLCS is asserted, how long does it take to FLAG signal to be valid?
In the figure 11 in [1, page 22] it seems to be valid one cycle after SLWR asserted (or what does the dashed line from the rising edge of PCLK mean?).  The table 10 in [1, page 22] notes three cycles latency from ADDR to DATA/FLAG.

3. Is possible to have more FLAGS than two actually provided by the slave FIFO interface (e. g. for every thread)?  If so, what changes are necessary to make?

I would like to have the throughput as high as possible without unnecessary waiting cycles.

I am looking forward to your answers.

Thank you,

Denis

Denis,
Please see my responses embedded below:
1. Is possible to assert SLWR simultaneously with SLCS (with ADDR and DATA IN loaded), or is it necessary to assert SLCS at least one cycle before asserting SLWR?
SLCS and SLWR can be asserted at the same time. But please note that the address setup time requirement (tAS) must be met, with respect to SLWR.

2. When ADDR is set and SLCS is asserted, how long does it take to FLAG signal to be valid?
In the figure 11 in [1, page 22] it seems to be valid one cycle after SLWR asserted (or what does the dashed line from the rising edge of PCLK mean?).  The table 10 in [1, page 22] notes three cycles latency from ADDR to DATA/FLAG.
There is a 3 cycle latency from address to FLAG valid. In Figure 11 in the datasheet, please note that there is already a latency shown between SLCS and SLWR, hence the FLAG is valid one cycle after SLWR.
To be very clear, if FX3 samples the address on CLK edge 1 (i.e. address is setup tAS before edge 1), then the valid FLAG can be sampled by external device on CLK edge 3.

3. Is possible to have more FLAGS than two actually provided by the slave FIFO interface (e. g. for every thread)?  If so, what changes are necessary to make?
Yes, it is possible to have a dedicated FLAG for each thread. Certain FX3 registers need to be set to achieve this. A FX3 SDK may be made available to you if you don't already have it, which will provide you with APIs to write these registers. Once you have this SDK, I can give you the exact registers and register values to be written. If you do not have the SDK, we will put  you in touch with the right person to get the SDK.

Thanks,
Sonia.

Sonia,

thank you very much for your answers and I enclose more quetions :-)

Ad 2. Is the three-cycle latency present even for dedicated FLAGs, or only for current thread FLAG (which depends on the address)?

Ad 3. The version of FX3 SDK I have downloaded (according to http://www.cypress.com/?app=forum&rID=51892) is 1.0 Beta1 and the version of GPIF I IDesigner is 0.7 Beta (plugins: CyProjectMgmtPlugin, Gpif2Model, CodeGenerator, Gpif2Views, Gpif2LibViews, Gpif2 Timing Model).

Best regards,

Denis

Hi Denis,

The three cycle latency from ADDR to FLAG is only for "current thread" FLAGs. FLAGs dedicated to a particular thread will always show the status of the socket associated with that thread.

A Beta2 release of the SDK was posted on the ftp site a couple days ago. Please make sure you get that release.

Thanks,

Sonia.

hi sonia:

how can i get more flag for slave fifo?