Hi everybody,

I am new to this forum so I am trying to explain my Problem as detailed as possible. If you need more information don't mind asking me.

First of all I want to connect a FPGA to a virtual COM Port via FX2LP. I started with the application note mentioned above. My configuration is working quite correct, but the FX2LP is not taking the correct data from the FD0-7 Pins. The data printed on the Hyperterminal are an alternating pattern 2 and ┼ .

I will post my configuration of the FX2LP and the Timing recorded by oscilloscope tomorrow.

Did anybody else have a similar problem?

Thanks and best regards.

Hi again,

I think I posted on the wrong place of the forum. If yes, please move it to the correct place.
 

Now my changed code parts: 

void TD_Init(void) // Called once at startup
{


// set the CPU clock to 48MHz
//CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1) ;
CPUCS = 0x12;

// set the slave FIFO interface to 48MHz
//IFCONFIG |= 0x40;
//IFCONFIG |= 0xE3; // Interface set to 48 MHz and IFCLK output is driven (IFCLKSRC=1,3048MHZ=1,IFCLKOE=1,IFCLKPOL=0)
IFCONFIG |= 0xF3; // Interface set to 48 MHz and IFCLK output is driven (IFCLKSRC=1,3048MHZ=1,IFCLKOE=1,IFCLKPOL=1)
//IFCONFIG |= 0xB3; // Interface set to 30 MHz and IFCLK output is driven (IFCLKSRC=1,3048MHZ=0,IFCLKOE=1,IFCLKPOL=1)
SYNCDELAY;
REVCTL = 0x03; // Disabled Autoarming & Enabled Enhanced Packet Handling
SYNCDELAY;

PINFLAGSAB = 0x0B; // FLAGA - EP8 Empty Flag
SYNCDELAY;
PINFLAGSCD = 0x0F; // FLAGC - EP8 Full Flag
SYNCDELAY;

PORTACFG |= 0x00;

EP1OUTCFG = 0xA0; // Configure EP1OUT as BULK EP (VALID=1,TYPE1=1)
SYNCDELAY;
EP1INCFG = 0xB0; // Configure EP1IN as BULK IN EP (VALID=1,TYPE1=1,TYPE0=1) means Interrupt-EP according to TRM
SYNCDELAY; // see TRM section 15.14
EP2CFG = 0x7F; // Invalid EP
SYNCDELAY;
EP4CFG = 0x7F; // Invalid EP
SYNCDELAY;
EP6CFG = 0x7F; // Invalid EP
SYNCDELAY;

EP8CFG = 0xE0; // Configure EP8 as BULK IN EP with 512bytes size and Quad-Buffering
SYNCDELAY;

FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions
SYNCDELAY; // see TRM section 15.14
FIFORESET = 0x08; // reset, FIFO 8
SYNCDELAY; //
FIFORESET = 0x00; // deactivate NAK-ALL
SYNCDELAY;

// Configure all Fifos with (wordwide=0) to be able to use the FD[8:15] as PortD for debuggin purposes
EP2FIFOCFG = 0x00; // Configure EP2 FIFO in 8-bit mode
SYNCDELAY;
EP4FIFOCFG = 0x00; // Configure EP4 FIFO in 8-bit mode
SYNCDELAY;
EP6FIFOCFG = 0x00; // Configure EP6 FIFO in 8-bit mode
SYNCDELAY;

// Configure EP8
//EP8FIFOCFG = 0x4C; // Configure EP8 FIFO in 8-bit Auto Commit mode (ZEROLENIN=1)
EP8FIFOCFG = 0x48; // Configure EP8 FIFO in 8-bit Auto Commit mode (ZEROLENIN=0)
SYNCDELAY;

// Set Auto-Commit length to 1 byte
EP8AUTOINLENH = 0x00;
SYNCDELAY;
EP8AUTOINLENL = 0x01;
SYNCDELAY;

//Serial0Init(); // Initialize the Serial Port 0 for the Communication
IOInit();

}
 

void TD_Poll(void) // Called repeatedly while the device is idle
{

// Serial State Notification that has to be sent periodically to the host

if (!(EP1INCS & 0x02)) // check if EP1IN is available
{
EP1INBUF[0] = 0x0A; // if it is available, then fill the first 10 bytes of the buffer with
EP1INBUF[1] = 0x20; // appropriate data.
EP1INBUF[2] = 0x00;
EP1INBUF[3] = 0x00;
EP1INBUF[4] = 0x00;
EP1INBUF[5] = 0x00;
EP1INBUF[6] = 0x00;
EP1INBUF[7] = 0x02;
EP1INBUF[8] = 0x00;
EP1INBUF[9] = 0x00;
EP1INBC = 10; // manually commit once the buffer is filled
}

// recieving the data from the USB Host and send it out

if (!(EP1OUTCS & 0x02)) // Check if EP1OUT is available

{
WriteByteS0(EP1OUTBUF[0]);
EP1OUTBC = 0x04;
}

}
 

This is all I have changed from the original code. Except the WriteByteS0 function which now outputs to the digital IO Pins of Port D. In the original example EP8 was used to transfer data to the host, which I am trying to use for Slave Fifo IN to get my data from the FPGA to the Host. 

 I tried different input bytes, but the pattern transmitted does not change. So I wondered, whether I need the SLCS# signal to activate the FD00-7 Pins. Normally the Pin PA.7 is usable as digital IO, FlagD or SLCS#. At the moment the PORTACFG is configured that PA.7 is used as digital IO. What is the state of the SLCS# internally, if the signal is not routed outside? I did not find any information about that in TRM and in datasheet either.

I appreciate help of any kind and will put the timing recorded by oscilloscope online tomorrow.

Best regards

 Hello test666,

First, regarding the state of the SLCS# signal. This signal is used for sharing the Io bus between multiple slaves. The signal is also usable as digital IO. From PORTACFG |= 0x00, it is clear that you are using it like digital IO only. In this case there is no need of explicitly grounding that pin, since you are not using that signal as SLCS#.

The explicit grounding of this signal is required, if this signal is selected as SLCS in PORTACFG, but is only used for EZ-USB slave FIFO interface, without any other slaves. This explains.

Now regarding the junk characters you are getting on the serial terminal, we have seen it usually due to the baud-rate mismatch. The baud-rate can very depending on the clock speed. 

Since your last response was on 3'rd, is there any progress thereafter? let me know if you still have the issues.

Thanks,

Samir

Hello Samir, 

thank you very much for your answer. So the SLCS# function is clear to me.

And yes there is further progress. I took two recordings on the signal timing between FPGA and the FX2. The scope_0 shows the rebuilded version of the streaming example from the application note. The other picture was taken today after I rebuild my VHDL module with registered outputs. Are the timings correct?

In the datasheet the timing is shown regarding to IFCLK. Is the timing the same, when I use the inverted output? Or is the timing then related to CLKOUT, which is not inverted?
 

You mentioned the baudrate as a possible reason for my junk characters, but I don't use the hardware UART of the FX. After the decoding of the optional hardware UART the decoded byte is sent over USB. When the baudrate changes only the hardware UART settings are changed and the decoded byte stays the same (if the sender corrects the baudrate too). And as I want to use the slave FIFO the baudrate should be irrelevant, shouldn't it?

Thanks again for your help. I think there would be more feedback if this Thread would be put to the High Speed USB part of this forum.

Best regards

test666

And the other picture. 

What I forgot to mention is that it is not really junk I get in the Terminal. It is a sequence of two alternating signs. For example :$:$:$:$:$:$ and so on.

Best regards

test666 

Hello test666,

The problems you described here need some investigations and experiments. Please create a Cypress tech support case on this for better follow-up.

Hasib

I know this thread is a few months old, but I found it when I was having a similar problem of alternating data values.

The solution for me was to fix the endpoint configuration of all the endpoints so that they matched one of the 12 valid configurations in the EZ-USB TRM  section "1.18 EZ-USB Endpoint Buffers".

 Hello Dan,

Thank you for posting the solution here. It might help someone with similar issue.

Regards,

Gayathri