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Why the length of WR_FIFO is longer than what I want?
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Why the length of WR_FIFO is longer than what I want?

yxm posted on 01 Mar 2011 7:15 PM PST
Member
3 Forum Posts

I use the 68013A, GPIF mode, the FIFO write, found that each write of n data , the length of WR_FIFO signal is longer than n datas' length, the result is that n+1 datas wrote into the FIFO. why ?




Re: Why the length of WR_FIFO is longer than what I want?

Shub posted on 02 Mar 2011 01:20 AM PST
Cypress Employee
27 Forum Posts

Hi,

Please check whether you have a state after the WR_FIFO signal assertion which deasserts this signal and jump to the idele state after that stste.

Also if you can attach the firmware and gpif waveform I will be able to help you more on this.

-Shubham






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