Hello, I am developing a cypress FX2 firmware. I am using GPIF master mode. I have generated the waveform(single_read, single_write, FIFO_read, FIFO_write)using the GPIF_designer, single_read and single_write is ok, FIFO_read is almost ok except the actural wave number is half the c code defined, FIFO_write transaction counter does not decrease, the GPIFTRIG GPIF done bit is not set. so write cycle will not stop, can any one help?
Here is the code.
void TD_Init(void) // Called once at startup
{
// set the CPU clock to 48MHz
CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1);
SYNCDELAY;
EP2CFG = 0xA0;
SYNCDELAY;
EP4CFG = 0x00;
SYNCDELAY;
EP6CFG = 0xE0;
SYNCDELAY;
EP8CFG = 0x00;
SYNCDELAY;
FIFORESET = 0x80;
SYNCDELAY;
FIFORESET = 0x02;
SYNCDELAY;
FIFORESET = 0x06;
SYNCDELAY;
FIFORESET = 0x00;
SYNCDELAY;
EP2FIFOCFG = 0x01;
SYNCDELAY;
EP2FIFOCFG = 0x11;
SYNCDELAY;
EP6FIFOCFG = 0x09;
SYNCDELAY;
GpifInit (); // initialize GPIF registers
SYNCDELAY;
EP2GPIFFLGSEL = 0x01; // For EP2OUT, GPIF uses EF flag
SYNCDELAY;
EP6GPIFFLGSEL = 0x02; // For EP6IN, GPIF uses FF flag
SYNCDELAY;
}
void TD_Poll(void)
{
if( GPIFTRIG & 0x80 ) // if GPIF interface IDLE
{
if ( ! ( EP24FIFOFLGS & 0x02 ) ) // if there's a packet in the peripheral domain for EP2
{
if ( GPIFREADYSTAT&0x02 ) // if the external FIFO is not full EXTFIFONOTFULL
{
SYNCDELAY;
GPIFTCB1 = 0x01; // setup transaction count (512 bytes/2 for word wide -> 0x0100)
SYNCDELAY;
GPIFTCB0 = 0x00;
SYNCDELAY;
GPIFTRIG = GPIF_EP2; // launch GPIF FIFO WRITE Transaction from EP2 FIFO
SYNCDELAY;
//FIFO write waveform is triggered, but nerver done, why?
while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 GPIF Done bit
{
; // the code will stop here
}
SYNCDELAY;
}
}
}
}
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