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Behavior of CTL / FLAG pins in Port I/O Mode?
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Behavior of CTL / FLAG pins in Port I/O Mode?

NigelWA posted on 15 Jul 2010 10:36 AM PST

1 Forum Post

 

Hi all,

I'm using a CY7C68013a hi-speed USB interface chip.

According to the docs there are thee modes: Slave FIFO, GPIF Master, and Ports I/O

In Slave FIFO mode, the CTL/FLAG pins operate as FLAGA...FLAGC

In GPIF Mode, the pins operate as CTL0...CTL2 and are controlled by GPIFIDLECTL ( except when doing a transaction )

... My question is what these three pins do when in Ports I/O mode? - are they tri-state or under control of GPIFIDLECTL,... ?

Also - do writes to GPIFIDLECTL have immediate effect (on these pins)when in GPIF idle mode or is that sampled when entering idle mode?

- Thanks!

 

 







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