Hi, all
I am interfacing the Cypress EZ-USB FX2LP (Cy7C68013A) to a Lattice FPGA. The data is transferred from FPGA through the slave FIFO interface in AUTOIN mode (auto-commit with size of 1024-byte) to PC.

Endpoint 2 is used, the fifo uses double buffering with packet size of 1024 bytes. The external interface is set to 16 bits wide. The interface clock IFCLK is driven by the FPGA, and is inverted internally in the FX2 (through IFCONFIG setting). Clock frequency is 48 MHz. Initialization of the endpoint buffer is performed as directed by the example provided in the EZ-USB technical reference manual.

The observed behavior is that, PC is waitting for data of usb ,when a 2048-byte packet is pushed to the slave fifo interface, it is tansferred to the USB domain and read by the PC. After two packets is read, the FX2 reports that the FIFO is not empty.At that point reading EP2FIFOBCH:L reports that the FIFO contains 62 bytes of data, which was never explicitly pushed to the slave fifo by the FPGA.

Has anyone encountered problems like this before, and has he been able to solve them?

I would appreciate any help.

You've not posted your code snippet here.... I'm just guessing.... Maybe you have not ARMed the endpoint by writing 0x80 to EP2BCL or writing to INPKTEND while configuring the endpoint... you can look up the examples that come with the DVK to understand what i'm talking about....

If you are doing it can you post ur code snippet of configuring/ARMing of endpoint here... Also configure the endpoint as say quad buffered and let me know what you are observing....

Thank you.Here is a piece of my code.

void TD_Init( void )
{

  CPUCS = 0x10;                 // CLKSPD[1:0]=10, for 48MHz operation
  SYNCDELAY;

  REVCTL=0X03;
  SYNCDELAY;

 SYNCDELAY;
  FIFORESET = 0x80;             
  SYNCDELAY;                    // see TRM section 15.14
  FIFORESET = 0x02;             // reset, FIFO 2
  SYNCDELAY;                    //
  FIFORESET = 0x04;             // reset, FIFO 4
  SYNCDELAY;                    //
  FIFORESET = 0x06;             // reset, FIFO 6
  SYNCDELAY;                    //
  FIFORESET = 0x08;             // reset, FIFO 8
  SYNCDELAY;                    //
  FIFORESET = 0x00;           
  SYNCDELAY;

   EP2CFG=0XEA;
  SYNCDELAY;
  EP6CFG=0XEA;
  SYNCDELAY;

  EP4CFG=0X00;
  SYNCDELAY;
  EP8CFG=0X00;
  SYNCDELAY;
 
  //IFCONFIG = 0xCB;          
  IFCONFIG = 0x43;            
  SYNCDELAY; 
  // IFCLKSRC=0   , FIFOs executes on external clk source
  // xMHz=0       , 48MHz internal clk rate
  // IFCLKOE=0    , Don't drive IFCLK pin signal at 48MHz
  // IFCLKPOL=0   , Don't invert IFCLK pin signal from internal clk
  // ASYNC=1      , master samples asynchronous
  // GSTATE=0     , Don't drive GPIF states out on PORTE[2:0], debug WF
  // IFCFG[1:0]=11, FX2 in slave FIFO mode

  EP2FIFOCFG = 0x09;            // AUTOIN=1, ZEROLENIN=1,WORDWIDE=1
  SYNCDELAY;
 
  EP6FIFOCFG = 0x09;            // AUTOIN=1, ZEROLENIN=1,WORDWIDE=1
  SYNCDELAY;

   
  EP4FIFOCFG = 0x00;            // AUTOIN=0, ZEROLENIN=0,WORDWIDE=0
  SYNCDELAY;

  EP8FIFOCFG = 0x00;            // AUTOIN=0, ZEROLENIN=0,WORDWIDE=0
  SYNCDELAY;

 
  PINFLAGSAB=0X00;
  SYNCDELAY;
  PINFLAGSCD=0X00;
  SYNCDELAY;
 

  PORTACFG = 0x40;         
  SYNCDELAY;
  PORTCCFG=0x00;      
  SYNCDELAY;
  PORTECFG=0x00;
  SYNCDELAY;
  OEC=0XFF;   
  SYNCDELAY;
  IOC=0xFF;  
  SYNCDELAY;

  //SLAVE FIFO 
  FIFOPINPOLAR=0X00;
  //FIFOPINPOLAR=0X01;
  SYNCDELAY;

  //AUTOIN
  EP2AUTOINLENH=0X04;
  SYNCDELAY;
  EP2AUTOINLENL=0X00;
  SYNCDELAY;
  EP6AUTOINLENH=0X04;
  SYNCDELAY;
  EP6AUTOINLENL=0X00;
  SYNCDELAY;

  EP4AUTOINLENH=0X00;
  SYNCDELAY;
  EP4AUTOINLENL=0X00;
  SYNCDELAY;
  EP8AUTOINLENH=0X00;
  SYNCDELAY;
  EP8AUTOINLENL=0X00;
  SYNCDELAY;
 
  Rwuen = TRUE;
 
  addrcmd=0x00;     //命令端口初始化
 
}
 

Since you are configuring both endpoint as IN i don't think ARMing the endpoint is the problem. One thing i would do is avoid writing to registers corresponding to EP4 and EP8 since they are not used here.

I have masked the writing on EP4 and EP8 registers, but the problem still exists.

Actually,my application on Cy68013A is quite simple:

EP2 and EP6 is configured as IN with double buffering using auto-commit -in size of 1024 bytes under the slave FIFO interface mode.

External FPGA pushs a 2048-byte packet data  into EP2 and EP6 ALTERNATELY according to FLAG C in the slave fifo interface.

The observed prolblem is that , after some 2048-byte packets data of EP2 and EP6 are correctly transferred to PC, the FX2 reports that the fifo is not empty. At that  point ,EP2FIFOBCH:L indicates that FIFO contains  less than 1024-byte of data.FLAG C can not assert the external FPGA to continue pushing data.

Looks like we've not isolated the problem yet...

Here are a few things that you can do to isolate the issue...

1. Are you able to transfer only 2048 bytes or are you able to transfer data constantly and somewhere in the middle it stops?

2. Are you able to constantly transfer through EP6 without this prob?

3. Read EP2BCH and EP2BCL to see if the packet has been committed?

4. Are you sure there are no glitches on the hardware line?

1.We can transfer a few blocks of 2048-byte size of data constantly and stop somwhere in the middle of data transportation.

2.Because transferring data through EP2 and EP6 alternately, external logic must wait before the EP2 data is pushed into slave fifo interface completely. The Sequence looks like EP2->EP6->EP2->EP6......

3.When the problem occurs,EP2FIFOBCH:L reports  that there are some data in EP2 fifo. Why do we see EP2BCH:L rather than EP2FIFOBCH:L? Would you tell me the differences of EP2BCH:L and EP2FIFOBCH:L? By the way ,in bulk mode transferring, can we configure the EP2 auto-in length as 1024-byte?

Looking at your description one of two things might be happening...There might be a glitch on the hardware interface making FX2LP think that data is being driven by the FPGA though it is not.

1. So FX2LP is waiting for more data from the FPGA to commit the packet...

2. or FX2LP committed a packet of 62 due to signals at the hardware interface

EP2FIFOBCH:L gives the number of bytes in EP2 buffer but doesn't say if the buffer is free or committed... EP2BCH:L will tell you that... if 2 is the case then you should be able to see the empty flag assert since the packet is committed and the 62 byte packet would be read by the host...

if the host did try to read and EP2 NAKed then it is 1.... did you try reading EP2 from the host when this happens??

Before FPGA pushs first block 1024-byte data into slave FIFO, EP2BCH:L reports 47:63.

After FPGA drives first block 1024-byte data into slave FIFO, EP2BCH:L indicates ED:2F and EP2CS is 10

Why EP2BCH:L is not 04:00 (i.e.1024)?

Best regards

Sounds interesting.

I don't have necessary hardware at my end at this point of time. I'll check if i can setup a board at my end and replicate this issue.

would you tell me something wrong in my 56pvxc firmware code:

  PINFLAGSAB = 0xE6;            //   *****Original 0xE6
  SYNCDELAY;
  PINFLAGSCD = 0xF8;            //   *****original 0xF8
  SYNCDELAY;
  PORTACFG |= 0x40;             // original 0x00；edit to 0x40 by lw for confilct with flash!!!!
  SYNCDELAY;

use this firmware,the flash does not confilect whit usb ,both of them are connecting dsp with emif on my board.
but i find the flaga and flagc can't work well. please give me a hand,thank you.

Hi,

What exactly is the faulty behavior that you're observing?

Regards,

Anand

detail in the txt files.excuse me for my pool english...

usb works well in this code,but flash confilict with usb on data bus...

The only difference i can see between the two code is the PORTACFG setting.

You're enabling SLCS functionality in badcode.txt and not enabling it in goodcode.txt.

Is your device in slave fifo mode?

Are you using PA7 to control GPIO[13] of DSP? If so, what is the statement you are using to make it high or low?

Regards,

Anand

yes,my device is working in slave mode.

' to make it high or low',in my device,dsp use GPIO[13] to Select usb chip,High means write 1 and low means write 0.

through modifing the firmware,i just want my usb and flash to work well at the same time.

for example ,after dsp gets data from my pc software with usb bulk tranfer,dsp may write the data into Nor Flash.

in order to implement above ,how to edit my firmware code? thank you very much.

Hi,

The entire design has to be looked at to understand the conflict between the data bus and the usb bus. It would be too complex to discuss over forum and it easier if someone had a closer look at it.

Can you please create a tech support case on this (MyAccount -> MyCases).

Thanks,

Anand

no problem!many thanks...

hi,aasi

I have create my case( MyCase #: 489394-566040000.),thanks for your response

by the way,how long my case will get been resolved?

It kind of depends on the complexity of the issue. Once our engineers get to the cause of the issue it should get solved real fast.

Regards,

Anand

Hi,aasi

until now,my cases doen't get resolved.but i get a respons as following:

Hi Li,

What is the flash, you are talking about? Can you please give me a block diagram, so that it will be clear for understanding?

Do you want to modify the host PC data before writing to the flash/DSP?

Regards,
Gopal

would you give me a hand to let my cases to be resolved as soon as posible.thank you very much.

 

Hi,

Please post the responses to the questions asked in the case and our engineers will help you with the issue. They're just collecting basic information to understand the issue better so that they can help you better.

Regards,

Anand

hi,aasi

can you access mycases?would you help to modified my firmware,let it work cerrectly without confilcting with Nor Flash.

my dear cypress,don't let me be.thank you.