Cypress Perform

Home > Design Support > Cypress Developer CommunityTM > Cypress Forums > USB Controllers

Bookmark and Share
Cypress Developer CommunityTM
Forums | Videos | Blogs | Training | Rewards Program | Community Components



GPIF : extra active edges on strobe ???
Moderator:
RSKV

Post Reply
Follow this topic



GPIF : extra active edges on strobe ???

jsteele posted on 13 Jul 2009 12:04 PM PST

1 Forum Post
Hi,

In AN4051 (Doc No. 001-15284) about the GPIF Flow State feature for
UDMA, there is a strange (to me) quote on page 4 :

"It should be noted that in the case where MSTB is a CTL pin, the
GPIF will produce at most one extra active edge on MSTB in response to
a not ready indication from the slave."

So am I interpreting this correctly : if the GPIF is in a flow state
and reading data from an external slave, and the slave says "no data
available", then the GPIF *might* (or might not) go ahead and read the
data anyway ?


If this is the case, how does one deal with this situation ? In my
case, I'm reading from a FIFO inside an FPGA, so I can configure it to
have an "almost empty" flag in addition to an "empty flag". It would
seem that the logic would be to pass the FX2 a signal like :


RDY0 = (almost_empty) OR (empty),

and have the flowstate use RDY0 to throttle the data. In principle
this should transfer all but the final word from the FIFO. ("almost
empty" means there is one word remaining.) That, I suppose, could be
read from the FIFO by a normal (i.e., not flow-) state of the GPIF.


Is this the right approach ?

Unfortunately, I gave it a shot and it's not quite working yet.
Before pouring too much effort into it, I'd like to know if there's an
easier way...


BTW, I am basically just using the GPIF Primer example that
writes/reads to an external FIFO. I got rid of the OUT EP and the
write, and instead pipe external video data into the FIFO in the
FPGA. For the flow state logic I use

func = (FifoFlag) OR (empty),
if (func == 0) assert RE#, clock data
if (func == 1) de-assert RE#


where "FifoFlag" is the FX2's FULL flag for the IN EP, and "empty" is
the fpga FIFO empty flag.


Thanks





ALL CONTENT AND MATERIALS ON THIS SITE ARE PROVIDED "AS IS". CYPRESS SEMICONDUCTOR AND ITS RESPECTIVE SUPPLIERS MAKE NO REPRESENTATIONS ABOUT THE SUITABILITY OF THESE MATERIALS FOR ANY PURPOSE AND DISCLAIM ALL WARRANTIES AND CONDITIONS WITH REGARD TO THESE MATERIALS, INCLUDING BUT NOT LIMITED TO, ALL IMPLIED WARRANTIES AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHT. NO LICENSE, EITHER EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, IS GRANTED BY CYPRESS SEMICONDUCTOR. USE OF THE INFORMATION ON THIS SITE MAY REQUIRE A LICENSE FROM A THIRD PARTY, OR A LICENSE FROM CYPRESS SEMICONDUCTOR.

Content on this site may contain or be subject to specific guidelines or limitations on use. All postings and use of the content on this site are subject to the Terms and Conditions of the site; third parties using this content agree to abide by any limitations or guidelines and to comply with the Terms and Conditions of this site. Cypress Semiconductor and its suppliers reserve the right to make corrections, deletions, modifications, enhancements, improvements and other changes to the content and materials, its products, programs and services at any time or to move or discontinue any content, products, programs, or services without notice.

Spec No: None; Sunset Owner: KXP; Secondary Owner: VWA; Sunset Date: 01/01/20