hi guys,
recently, I'm developing a usb project, in which Cy7c68013A-128AXC is used to communicate with FPGA through slave fifo interface,
in the 68013, EP2 is configured as 512 bytes double buffered mannual out fifo, EP6 is configured as 512 byte double buffered auto-in fifo, IFCLK is coming from external.
after painful debugging, I saw very strange behavior in the slave fifo interface:
when FPGA read data from 68013 through slave fifo interface, we must set the SLOE bit of FIFOPINPOLAR register to be '1', after that, FPGA can correctly read data from slave fifo interface no matter what value appears in SLOE pin, even though drive '0' on SLOE pin.
otherwise, if we set the SLOE bit of FIFOPINPOLAR register to be '0', then we can never read data out from slave fifo even we drive SLOE pin to '0', the data bus on slave fifo looks like in HighZ state.
when FPGA write data into 68013, the condition is contrary to read data from 68013. we must set the SLOE bit of FIFOPINPOLAR register to be '0', after that, FPGA can correctly write data into 68013 through slave fifo interface no matter what value appears in SLOE pin, even though drive '0' on SLOE pin.
otherwise, if we set the SLOE bit of FIFOPINPOLAR register to be '1', then we can never write data into 68013 through slave fifo interface, even we drive SLOE pin to '0'.
and I'm sure that the SLOE pin connection is ok, it's not floating.
following is TD_init() in 68013 firmware, is there any wrong configuration??
void TD_Init(void) // Called once at startup
{
// set the CPU clock to 48MHz
CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1) ;
REVCTL = 0x03; // MUST set REVCTL.0 and REVCTL.1 to 1
SYNCDELAY; //
FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions
SYNCDELAY; //
FIFORESET = 0x02; // reset, FIFO 2
SYNCDELAY;
FIFORESET = 0x06; // reset, FIFO 6
SYNCDELAY; // //
FIFORESET = 0x00; // deactivate NAK-ALL
SYNCDELAY;
// set the slave FIFO interface to 48MHz, use external clock
IFCONFIG = 0x43;
SYNCDELAY;
EP2FIFOCFG = 0x01; // mannual out
SYNCDELAY;
EP2CFG = 0xA2;
SYNCDELAY;
EP6FIFOCFG = 0x09; // autoin
SYNCDELAY;
EP6CFG = 0xE2;
SYNCDELAY;
// !!!!!! when external fifo master read data from slave interface, the SLOE bit in register FIFOPINPOLAR must set to be 1, FIFOPINPOLAR = 0x10
// !!!!!! when external fifo master write data into slave interface, the SLOE bit in register FIFOPINPOLAR must set to be 0, FIFOPINPOLAR = 0x00
FIFOPINPOLAR = 0x00;
SYNCDELAY;
EP6AUTOINLENH = 0x02; // you can define these as you wish,
SYNCDELAY; // to have the FX2 automatically limit IN's
EP6AUTOINLENL = 0x00;
SYNCDELAY;
SYNCDELAY;
EP2BCL = 0x80; // arm EP2OUT by writing byte count w/skip.
SYNCDELAY;
EP2BCL = 0x80;
SYNCDELAY;
// enable dual autopointer feature
AUTOPTRSETUP |= 0x01;
Rwuen = TRUE; // Enable remote-wakeup
}
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