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Correction to my prior post. I forgot, frankly, the Timers do not have a separate capture register,
so was trying to advise you the compare register was pointless in the design to calc PW.
That being said I fooled around trying different approaches, looking at jitter, and seem to
think a slightly different approach produces a better result.
So I set up a timer, to capture on falling edge, and the input pin to the timer to ISR on rising edge.
In ISR for pin I simply read timer register. In capture ISR I do not read the compare register,
I execute again a simple read on timer register. So I have two values, and keep the timer running
continuously. Reason I did not read the capture register for second value is I felt that the machine
cycles, latency, is same for both ISR calls. So my observed jitter was better with this approach.
I worked with pulses up to 10 Khz with a 1 uS timer clock. And PW down to 30 uS in width,
where error seemed too high. I have not tried faster Timer clock, say 12 Mhz, to see what that will do.
I then tried using a counter solution, just one ISR on GPIO negative edge that feeds counter enable.
Pulse coming in goes high, starts counter counting. ISR stops counter, reads it, reloads it, restarts it.
Net result seemed I could handle much narrower pulses, 10 uS reading accurately.
Food for thought, Dana.
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