hi developers,

                             i am about to design a PSoC based board. I am implementing the manual reset and the ISSP functionality in the board.  the connections i have made on the xres pin are as follows. the xres pin is connected to ground through a 10K pull- down resistor. the same pin is also connected to an ISSP header pin 3. is this a valid connection. can both functions exist without any interferrence?

Though I havent designed PSoC 1 boards,but whever we are dealing with multiple sources of reset,you should add a diode across them.

Lemme see if I can draw up what I mean.

It is a valid design when you're using a diode. By default you don't need to put an external resistor to ground to XRES as it has a builtin pull-down resistor. What's the device you're using? I haven't checked if there's a different implementation but for the ones I've used, XRES is active HIGH.

 hi developers,

          thanks for your valuable guidance. by the way the device i am using is CY8C29466. as per the data sheet it is an active high reset type. but would the diode drop cause any problem if  i am using a 5V to reset a device having Vdd supply also at 5V.

The diode affects noise margin, Vil spec is <= .8 V. So best to use a schottky

and make sure your noise at pin under control. Or use a N jFet open drain

or NPN Bipolar open collector ( R in base lead to limit current) or small signal

mosfet open drain to get a better "0" level.

Regards, Dana.

I just had my own experience trying something similar with the/ XRES pin on a PSoC-5. I tied the /XRES pin high (3.3v) through 10k resistor and then also tied the /XRES to a N.O. push-button that was ground on the opposite side of the contact from the XRES acting as a master reset PB. In addition to the push button and resistor, the XRES also connected to a system wide "RESET" bus where it made connection to /MCLR on a dsPIC30F4011, and /RESET on a RF300PD1 and /RESET on a DNT900 all sharing this common "master-reset" line. With 20/20 hind site, I would strongly recommend NOT trying this for several reasons. One reason is that my documentation indicates (which I found after the fact) that the reset (/MCLR) line on the dsPIC is elevated to around 12V+ during programming. Secondly, I was told that the PSOC-5 I used (CY8C5567-axi-019 I think) already had an internal pull up resistor. Subsequent review of the CY8CKIT-050 reference design schematic reviealed no need for an EXTERNAL pullup resistor (or pull down for that matter) on the /XRES pin. I had a hard time geting the miniprog-3 to acquire the PSoC on my design until after much trouble shooting when I decided to simply tie the /XRES pin on the PSOC5 to a programming header on one of my prototypes as well as aN.O. push button for manual RESET over-ride, but WITHOUT the pullup resistor installed,  as it wasn't shown on the CY8CKIT-050 reference design. Before making these changes, I decided to buy the CY8CKIT-050 at the advice of tech support so I could review a working system and compare it to mine so as to locate the source of my difficulties before making these changes.After the development kit arrived, I plugged it in just as I did my own prototype and I found it to work just fine by itself with the Miniprog-3. Without knowing much about the development board before it arrived, I was surprised to later see many similariries between the -050 and my prototype including a dedicated 2x16 character display port and two larger IO connectors for interconnecting to external circuits/systems. These similarities made comparison and troubleshooting against my own prototype system pretty straight forward and was well worth the money I spent compared to how much time I spent prior going in circles trying to identify to source of my problem.

The TRM (Technical Reference Manual) has a significant amount of info

on XRES and its behaviour, so I would suggest a look. Extracted from

it -

30.4.2 External Reset

An External Reset (XRES) is caused by pulling the XRES
pin high. The XRES pin has an always-on, pull down resis-
tor, so it does not require an external pull down for operation
and can be tied directly to ground or left open. Behavior after
XRES is similar to POR.

30.2.2 GPIO Behavior on External Reset

During External Reset (XRES=1), both P1[0] and P1[1] drive
resistive low (0). After XRES de-asserts, these pins continue
to drive resistive low for another 8 sleep clock cycles
(approximately 200 us). After this time, both pins transition
to a high impedance state and normal CPU operation
begins. This is illustrated in Figure 30-2.

Notice there seems some confusion, that pin has always on pulldown,
but goes to hi Z, maybe we ought to have tech support clarify this.

Regards, Dana.